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dmaengine: dw-edma: Join read/write channels into a single device
There is no point in splitting read/write channels. First of all, eDMA read and write channels belong to one physical controller. Secondly, channel differentiation can be done by filtering and dma_get_slave_caps(). Finally, having these channels handled separately needlessly complicates the code and causes this debugfs warning: debugfs: Directory '1f052000.pcie' with parent 'dmaengine' already present! Join the read/write channels into a single DMA device. Client drivers can choose the correct channel via the DMA slave direction setting. The default value is overridden by the dw_edma_device_caps() callback in accordance with the channel type. Link: https://lore.kernel.org/r/20230113171409.30470-18-Sergey.Semin@baikalelectronics.ru Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
parent
d015216853
commit
3883d64449
2 changed files with 61 additions and 60 deletions
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@ -208,6 +208,24 @@ static void dw_edma_start_transfer(struct dw_edma_chan *chan)
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desc->chunks_alloc--;
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}
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static void dw_edma_device_caps(struct dma_chan *dchan,
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struct dma_slave_caps *caps)
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{
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struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
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if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) {
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if (chan->dir == EDMA_DIR_READ)
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caps->directions = BIT(DMA_DEV_TO_MEM);
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else
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caps->directions = BIT(DMA_MEM_TO_DEV);
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} else {
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if (chan->dir == EDMA_DIR_WRITE)
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caps->directions = BIT(DMA_DEV_TO_MEM);
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else
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caps->directions = BIT(DMA_MEM_TO_DEV);
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}
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}
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static int dw_edma_device_config(struct dma_chan *dchan,
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struct dma_slave_config *config)
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{
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@ -717,8 +735,7 @@ static void dw_edma_free_chan_resources(struct dma_chan *dchan)
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}
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}
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static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
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u32 wr_alloc, u32 rd_alloc)
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static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc)
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{
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struct dw_edma_chip *chip = dw->chip;
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struct dw_edma_region *dt_region;
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@ -726,27 +743,15 @@ static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
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struct dw_edma_chan *chan;
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struct dw_edma_irq *irq;
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struct dma_device *dma;
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u32 alloc, off_alloc;
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u32 i, j, cnt;
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int err = 0;
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u32 i, ch_cnt;
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u32 pos;
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if (write) {
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i = 0;
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cnt = dw->wr_ch_cnt;
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dma = &dw->wr_edma;
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alloc = wr_alloc;
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off_alloc = 0;
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} else {
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i = dw->wr_ch_cnt;
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cnt = dw->rd_ch_cnt;
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dma = &dw->rd_edma;
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alloc = rd_alloc;
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off_alloc = wr_alloc;
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}
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ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
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dma = &dw->dma;
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INIT_LIST_HEAD(&dma->channels);
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for (j = 0; (alloc || dw->nr_irqs == 1) && j < cnt; j++, i++) {
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for (i = 0; i < ch_cnt; i++) {
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chan = &dw->chan[i];
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dt_region = devm_kzalloc(dev, sizeof(*dt_region), GFP_KERNEL);
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@ -756,52 +761,62 @@ static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
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chan->vc.chan.private = dt_region;
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chan->dw = dw;
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chan->id = j;
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chan->dir = write ? EDMA_DIR_WRITE : EDMA_DIR_READ;
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if (i < dw->wr_ch_cnt) {
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chan->id = i;
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chan->dir = EDMA_DIR_WRITE;
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} else {
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chan->id = i - dw->wr_ch_cnt;
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chan->dir = EDMA_DIR_READ;
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}
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chan->configured = false;
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chan->request = EDMA_REQ_NONE;
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chan->status = EDMA_ST_IDLE;
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if (write)
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chan->ll_max = (chip->ll_region_wr[j].sz / EDMA_LL_SZ);
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if (chan->dir == EDMA_DIR_WRITE)
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chan->ll_max = (chip->ll_region_wr[chan->id].sz / EDMA_LL_SZ);
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else
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chan->ll_max = (chip->ll_region_rd[j].sz / EDMA_LL_SZ);
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chan->ll_max = (chip->ll_region_rd[chan->id].sz / EDMA_LL_SZ);
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chan->ll_max -= 1;
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dev_vdbg(dev, "L. List:\tChannel %s[%u] max_cnt=%u\n",
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write ? "write" : "read", j, chan->ll_max);
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chan->dir == EDMA_DIR_WRITE ? "write" : "read",
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chan->id, chan->ll_max);
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if (dw->nr_irqs == 1)
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pos = 0;
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else if (chan->dir == EDMA_DIR_WRITE)
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pos = chan->id % wr_alloc;
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else
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pos = off_alloc + (j % alloc);
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pos = wr_alloc + chan->id % rd_alloc;
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irq = &dw->irq[pos];
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if (write)
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irq->wr_mask |= BIT(j);
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if (chan->dir == EDMA_DIR_WRITE)
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irq->wr_mask |= BIT(chan->id);
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else
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irq->rd_mask |= BIT(j);
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irq->rd_mask |= BIT(chan->id);
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irq->dw = dw;
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memcpy(&chan->msi, &irq->msi, sizeof(chan->msi));
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dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=0x%.8x%.8x, data=0x%.8x\n",
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write ? "write" : "read", j,
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chan->dir == EDMA_DIR_WRITE ? "write" : "read", chan->id,
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chan->msi.address_hi, chan->msi.address_lo,
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chan->msi.data);
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chan->vc.desc_free = vchan_free_desc;
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vchan_init(&chan->vc, dma);
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if (write) {
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dt_region->paddr = chip->dt_region_wr[j].paddr;
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dt_region->vaddr = chip->dt_region_wr[j].vaddr;
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dt_region->sz = chip->dt_region_wr[j].sz;
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if (chan->dir == EDMA_DIR_WRITE) {
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dt_region->paddr = chip->dt_region_wr[chan->id].paddr;
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dt_region->vaddr = chip->dt_region_wr[chan->id].vaddr;
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dt_region->sz = chip->dt_region_wr[chan->id].sz;
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} else {
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dt_region->paddr = chip->dt_region_rd[j].paddr;
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dt_region->vaddr = chip->dt_region_rd[j].vaddr;
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dt_region->sz = chip->dt_region_rd[j].sz;
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dt_region->paddr = chip->dt_region_rd[chan->id].paddr;
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dt_region->vaddr = chip->dt_region_rd[chan->id].vaddr;
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dt_region->sz = chip->dt_region_rd[chan->id].sz;
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}
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dw_edma_v0_core_device_config(chan);
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@ -813,7 +828,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
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dma_cap_set(DMA_CYCLIC, dma->cap_mask);
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dma_cap_set(DMA_PRIVATE, dma->cap_mask);
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dma_cap_set(DMA_INTERLEAVE, dma->cap_mask);
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dma->directions = BIT(write ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV);
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dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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dma->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
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@ -822,6 +837,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
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dma->dev = chip->dev;
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dma->device_alloc_chan_resources = dw_edma_alloc_chan_resources;
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dma->device_free_chan_resources = dw_edma_free_chan_resources;
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dma->device_caps = dw_edma_device_caps;
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dma->device_config = dw_edma_device_config;
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dma->device_pause = dw_edma_device_pause;
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dma->device_resume = dw_edma_device_resume;
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@ -835,9 +851,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, bool write,
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dma_set_max_seg_size(dma->dev, U32_MAX);
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/* Register DMA device */
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err = dma_async_device_register(dma);
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return err;
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return dma_async_device_register(dma);
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}
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static inline void dw_edma_dec_irq_alloc(int *nr_irqs, u32 *alloc, u16 cnt)
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@ -982,13 +996,8 @@ int dw_edma_probe(struct dw_edma_chip *chip)
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if (err)
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return err;
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/* Setup write channels */
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err = dw_edma_channel_setup(dw, true, wr_alloc, rd_alloc);
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if (err)
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goto err_irq_free;
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/* Setup read channels */
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err = dw_edma_channel_setup(dw, false, wr_alloc, rd_alloc);
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/* Setup write/read channels */
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err = dw_edma_channel_setup(dw, wr_alloc, rd_alloc);
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if (err)
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goto err_irq_free;
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@ -1022,15 +1031,8 @@ int dw_edma_remove(struct dw_edma_chip *chip)
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free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]);
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/* Deregister eDMA device */
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dma_async_device_unregister(&dw->wr_edma);
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list_for_each_entry_safe(chan, _chan, &dw->wr_edma.channels,
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vc.chan.device_node) {
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tasklet_kill(&chan->vc.task);
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list_del(&chan->vc.chan.device_node);
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}
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dma_async_device_unregister(&dw->rd_edma);
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list_for_each_entry_safe(chan, _chan, &dw->rd_edma.channels,
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dma_async_device_unregister(&dw->dma);
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list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
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vc.chan.device_node) {
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tasklet_kill(&chan->vc.task);
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list_del(&chan->vc.chan.device_node);
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@ -98,10 +98,9 @@ struct dw_edma_irq {
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struct dw_edma {
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char name[20];
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struct dma_device wr_edma;
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u16 wr_ch_cnt;
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struct dma_device dma;
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struct dma_device rd_edma;
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u16 wr_ch_cnt;
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u16 rd_ch_cnt;
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struct dw_edma_irq *irq;
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