ARM: SoC fixes for v4.1
Here's the usual "low-priority fixes that didn't make it into the last
few -rcs, with a twist: We had a fixes pull request that I didn't send
in time to get into 4.0, so we'll send some of them to Greg for -stable as
well.
Contents here is as usual not all that controversial:
- A handful of randconfig fixes from Arnd, in particular for older Samsung
platforms
- Exynos fixes, !SMP building, DTS updates for MMC and lid switch
- Kbuild fix to create output subdirectory for DTB files
- Misc minor fixes for OMAP
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Here's the usual "low-priority fixes that didn't make it into the last
few -rcs, with a twist: We had a fixes pull request that I didn't send
in time to get into 4.0, so we'll send some of them to Greg for
-stable as well.
Contents here is as usual not all that controversial:
- a handful of randconfig fixes from Arnd, in particular for older
Samsung platforms
- Exynos fixes, !SMP building, DTS updates for MMC and lid switch
- Kbuild fix to create output subdirectory for DTB files
- misc minor fixes for OMAP"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
ARM: at91/dt: sama5d3 xplained: add phy address for macb1
kbuild: Create directory for target DTB
ARM: mvebu: Disable CPU Idle on Armada 38x
ARM: DRA7: Enable Cortex A15 errata 798181
ARM: dts: am57xx-beagle-x15: Add thermal map to include fan and tmp102
ARM: dts: DRA7: Add bandgap and related thermal nodes
bus: ocp2scp: SYNC2 value should be changed to 0x6
ARM: dts: am4372: Add "ti,am437x-ocp2scp" as compatible string for OCP2SCP
ARM: OMAP2+: remove superfluous NULL pointer check
ARM: EXYNOS: Fix build breakage cpuidle on !SMP
ARM: dts: fix lid and power pin-functions for exynos5250-spring
ARM: dts: fix mmc node updates for exynos5250-spring
ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688
MAINTAINERS: add OMAP defconfigs under OMAP SUPPORT
ARM: OMAP1: PM: fix some build warnings on 1510-only Kconfigs
ARM: cns3xxx: don't export static symbol
ARM: S3C24XX: avoid a Kconfig warning
ARM: S3C24XX: fix header file inclusions
ARM: S3C24XX: fix building without PM_SLEEP
ARM: S3C24XX: use SAMSUNG_WAKEMASK for s3c2416
...
This commit is contained in:
Linus Torvalds
commit
38eb1dbb0d
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@ -1,7 +1,8 @@
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* OMAP OCP2SCP - ocp interface to scp interface
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properties:
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- compatible : Should be "ti,omap-ocp2scp"
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- compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
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Should be "ti,omap-ocp2scp" for all others
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- reg : Address and length of the register set for the device
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- #address-cells, #size-cells : Must be present if the device has sub-nodes
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- ranges : the child address space are mapped 1:1 onto the parent address space
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@ -7007,6 +7007,8 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
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S: Maintained
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F: arch/arm/*omap*/
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F: arch/arm/configs/omap1_defconfig
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F: arch/arm/configs/omap2plus_defconfig
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F: drivers/i2c/busses/i2c-omap.c
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F: drivers/irqchip/irq-omap-intc.c
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F: drivers/mfd/*omap*.c
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@ -796,7 +796,7 @@
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};
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ocp2scp0: ocp2scp@483a8000 {
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compatible = "ti,omap-ocp2scp";
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compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -815,7 +815,7 @@
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};
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ocp2scp1: ocp2scp@483e8000 {
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compatible = "ti,omap-ocp2scp";
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compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -87,6 +87,7 @@
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gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
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gpio-fan,speed-map = <0 0>,
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<13000 1>;
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#cooling-cells = <2>;
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};
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extcon_usb1: extcon_usb1 {
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@ -442,6 +443,7 @@
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pinctrl-0 = <&tmp102_pins_default>;
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interrupt-parent = <&gpio7>;
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interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
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#thermal-sensor-cells = <1>;
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};
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};
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@ -551,3 +553,50 @@
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&usb2 {
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dr_mode = "peripheral";
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};
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&cpu_trips {
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cpu_alert1: cpu_alert1 {
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temperature = <50000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "active";
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};
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};
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&cpu_cooling_maps {
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map1 {
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trip = <&cpu_alert1>;
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cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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&thermal_zones {
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board_thermal: board_thermal {
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polling-delay-passive = <1250>; /* milliseconds */
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polling-delay = <1500>; /* milliseconds */
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/* sensor ID */
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thermal-sensors = <&tmp102 0>;
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board_trips: trips {
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board_alert0: board_alert {
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temperature = <40000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "active";
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};
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board_crit: board_crit {
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temperature = <105000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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board_cooling_maps: cooling-maps {
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map0 {
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trip = <&board_alert0>;
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cooling-device =
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<&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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|
|
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@ -167,7 +167,13 @@
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macb1: ethernet@f802c000 {
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phy-mode = "rmii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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dbgu: serial@ffffee00 {
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|
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@ -185,6 +185,18 @@
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};
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};
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bandgap: bandgap@4a0021e0 {
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reg = <0x4a0021e0 0xc
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0x4a00232c 0xc
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0x4a002380 0x2c
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0x4a0023C0 0x3c
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0x4a002564 0x8
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0x4a002574 0x50>;
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compatible = "ti,dra752-bandgap";
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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#thermal-sensor-cells = <1>;
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};
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cm_core_aon: cm_core_aon@4a005000 {
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compatible = "ti,dra7-cm-core-aon";
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reg = <0x4a005000 0x2000>;
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@ -1435,6 +1447,17 @@
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status = "disabled";
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};
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};
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thermal_zones: thermal-zones {
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#include "omap4-cpu-thermal.dtsi"
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#include "omap5-gpu-thermal.dtsi"
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#include "omap5-core-thermal.dtsi"
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};
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};
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&cpu_thermal {
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polling-delay = <500>; /* milliseconds */
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};
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/include/ "dra7xx-clocks.dtsi"
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@ -20,6 +20,11 @@
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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/* cooling options */
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cooling-min-level = <0>;
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cooling-max-level = <2>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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@ -31,6 +31,11 @@
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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/* cooling options */
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cooling-min-level = <0>;
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cooling-max-level = <2>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu@1 {
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device_type = "cpu";
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@ -429,7 +429,6 @@
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&mmc_0 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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@ -437,11 +436,8 @@
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samsung,dw-mshc-ddr-timing = <1 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
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slot@0 {
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reg = <0>;
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bus-width = <8>;
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};
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bus-width = <8>;
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cap-mmc-highspeed;
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};
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/*
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@ -451,7 +447,6 @@
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&mmc_1 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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@ -459,11 +454,8 @@
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samsung,dw-mshc-ddr-timing = <1 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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bus-width = <4>;
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cap-sd-highspeed;
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};
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&pinctrl_0 {
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@ -490,7 +482,7 @@
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power_key_irq: power-key-irq {
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samsung,pins = "gpx1-3";
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samsung,pin-function = <0>;
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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@ -518,7 +510,7 @@
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lid_irq: lid-irq {
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samsung,pins = "gpx3-5";
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samsung,pin-function = <0>;
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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|
|
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|
|
@ -18,7 +18,7 @@ cpu_thermal: cpu_thermal {
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/* sensor ID */
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thermal-sensors = <&bandgap 0>;
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trips {
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cpu_trips: trips {
|
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cpu_alert0: cpu_alert {
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temperature = <100000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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@ -31,7 +31,7 @@ cpu_thermal: cpu_thermal {
|
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};
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};
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cooling-maps {
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cpu_cooling_maps: cooling-maps {
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map0 {
|
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trip = <&cpu_alert0>;
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cooling-device =
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|
|
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|
|
@ -73,7 +73,6 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block)
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__raw_writel(reg, PM_SOFT_RST_REG);
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}
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EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
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void cns3xxx_pwr_soft_rst(unsigned int block)
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{
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|
|
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|
|
@ -206,7 +206,7 @@ static void __init exynos_dt_machine_init(void)
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if (!IS_ENABLED(CONFIG_SMP))
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exynos_sysram_init();
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#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
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#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
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if (of_machine_is_compatible("samsung,exynos4210"))
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exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;
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#endif
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|
|
|
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|
|
@ -181,6 +181,7 @@ void exynos_enter_aftr(void)
|
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cpu_pm_exit();
|
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}
|
||||
|
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#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
|
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static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
|
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|
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static int exynos_cpu0_enter_aftr(void)
|
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|
|
@ -302,3 +303,4 @@ struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
|
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.pre_enter_aftr = exynos_pre_enter_aftr,
|
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.post_enter_aftr = exynos_post_enter_aftr,
|
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};
|
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#endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */
|
||||
|
|
|
|||
|
|
@ -415,6 +415,9 @@ static __init int armada_38x_cpuidle_init(void)
|
|||
void __iomem *mpsoc_base;
|
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u32 reg;
|
||||
|
||||
pr_warn("CPU idle is currently broken on Armada 38x: disabling");
|
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return 0;
|
||||
|
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np = of_find_compatible_node(NULL, NULL,
|
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"marvell,armada-380-coherency-fabric");
|
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if (!np)
|
||||
|
|
@ -476,6 +479,16 @@ static int __init mvebu_v7_cpu_pm_init(void)
|
|||
return 0;
|
||||
of_node_put(np);
|
||||
|
||||
/*
|
||||
* Currently the CPU idle support for Armada 38x is broken, as
|
||||
* the CPU hotplug uses some of the CPU idle functions it is
|
||||
* broken too, so let's disable it
|
||||
*/
|
||||
if (of_machine_is_compatible("marvell,armada380")) {
|
||||
cpu_hotplug_disable();
|
||||
pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling");
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("marvell,armadaxp"))
|
||||
ret = armada_xp_cpuidle_init();
|
||||
else if (of_machine_is_compatible("marvell,armada370"))
|
||||
|
|
@ -489,7 +502,8 @@ static int __init mvebu_v7_cpu_pm_init(void)
|
|||
return ret;
|
||||
|
||||
mvebu_v7_pmsu_enable_l2_powerdown_onidle();
|
||||
platform_device_register(&mvebu_v7_cpuidle_device);
|
||||
if (mvebu_v7_cpuidle_device.name)
|
||||
platform_device_register(&mvebu_v7_cpuidle_device);
|
||||
cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -71,13 +71,7 @@ static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
|
|||
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
|
||||
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
|
||||
|
||||
#ifndef CONFIG_OMAP_32K_TIMER
|
||||
|
||||
static unsigned short enable_dyn_sleep = 0;
|
||||
|
||||
#else
|
||||
|
||||
static unsigned short enable_dyn_sleep = 1;
|
||||
static unsigned short enable_dyn_sleep;
|
||||
|
||||
static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
|
||||
char *buf)
|
||||
|
|
@ -90,8 +84,9 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
|
|||
{
|
||||
unsigned short value;
|
||||
if (sscanf(buf, "%hu", &value) != 1 ||
|
||||
(value != 0 && value != 1)) {
|
||||
printk(KERN_ERR "idle_sleep_store: Invalid value\n");
|
||||
(value != 0 && value != 1) ||
|
||||
(value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
|
||||
pr_err("idle_sleep_store: Invalid value\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
enable_dyn_sleep = value;
|
||||
|
|
@ -101,7 +96,6 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
|
|||
static struct kobj_attribute sleep_while_idle_attr =
|
||||
__ATTR(sleep_while_idle, 0644, idle_show, idle_store);
|
||||
|
||||
#endif
|
||||
|
||||
static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
|
||||
|
||||
|
|
@ -115,16 +109,11 @@ void omap1_pm_idle(void)
|
|||
{
|
||||
extern __u32 arm_idlect1_mask;
|
||||
__u32 use_idlect1 = arm_idlect1_mask;
|
||||
int do_sleep = 0;
|
||||
|
||||
local_fiq_disable();
|
||||
|
||||
#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
|
||||
#warning Enable 32kHz OS timer in order to allow sleep states in idle
|
||||
use_idlect1 = use_idlect1 & ~(1 << 9);
|
||||
#else
|
||||
if (enable_dyn_sleep)
|
||||
do_sleep = 1;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OMAP_DM_TIMER
|
||||
|
|
@ -134,10 +123,12 @@ void omap1_pm_idle(void)
|
|||
if (omap_dma_running())
|
||||
use_idlect1 &= ~(1 << 6);
|
||||
|
||||
/* We should be able to remove the do_sleep variable and multiple
|
||||
/*
|
||||
* We should be able to remove the do_sleep variable and multiple
|
||||
* tests above as soon as drivers, timer and DMA code have been fixed.
|
||||
* Even the sleep block count should become obsolete. */
|
||||
if ((use_idlect1 != ~0) || !do_sleep) {
|
||||
* Even the sleep block count should become obsolete.
|
||||
*/
|
||||
if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
|
||||
|
||||
__u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
|
||||
if (cpu_is_omap15xx())
|
||||
|
|
@ -635,15 +626,25 @@ static const struct platform_suspend_ops omap_pm_ops = {
|
|||
|
||||
static int __init omap_pm_init(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
int error;
|
||||
#endif
|
||||
int error = 0;
|
||||
|
||||
if (!cpu_class_is_omap1())
|
||||
return -ENODEV;
|
||||
|
||||
printk("Power Management for TI OMAP.\n");
|
||||
pr_info("Power Management for TI OMAP.\n");
|
||||
|
||||
if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
|
||||
pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
|
||||
|
||||
if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
|
||||
pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
|
||||
|
||||
if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
|
||||
IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
|
||||
/* OMAP16xx only */
|
||||
pr_info("OMAP1 PM: sleep states in idle enabled\n");
|
||||
enable_dyn_sleep = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* We copy the assembler sleep/wakeup routines to SRAM.
|
||||
|
|
@ -693,17 +694,15 @@ static int __init omap_pm_init(void)
|
|||
omap_pm_init_debugfs();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
|
||||
if (error)
|
||||
printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
|
||||
#endif
|
||||
|
||||
if (cpu_is_omap16xx()) {
|
||||
/* configure LOW_PWR pin */
|
||||
omap_cfg_reg(T20_1610_LOW_PWR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return error;
|
||||
}
|
||||
__initcall(omap_pm_init);
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ config SOC_DRA7XX
|
|||
select ARM_GIC
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select IRQ_CROSSBAR
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
|
||||
config ARCH_OMAP2PLUS
|
||||
bool
|
||||
|
|
@ -278,27 +279,6 @@ config OMAP3_SDRC_AC_TIMING
|
|||
wish to say no. Selecting yes without understanding what is
|
||||
going on could result in system crashes;
|
||||
|
||||
config OMAP4_ERRATA_I688
|
||||
bool "OMAP4 errata: Async Bridge Corruption"
|
||||
depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
|
||||
select ARCH_HAS_BARRIERS
|
||||
help
|
||||
If a data is stalled inside asynchronous bridge because of back
|
||||
pressure, it may be accepted multiple times, creating pointer
|
||||
misalignment that will corrupt next transfers on that data path
|
||||
until next reset of the system (No recovery procedure once the
|
||||
issue is hit, the path remains consistently broken). Async bridge
|
||||
can be found on path between MPU to EMIF and MPU to L3 interconnect.
|
||||
This situation can happen only when the idle is initiated by a
|
||||
Master Request Disconnection (which is trigged by software when
|
||||
executing WFI on CPU).
|
||||
The work-around for this errata needs all the initiators connected
|
||||
through async bridge must ensure that data path is properly drained
|
||||
before issuing WFI. This condition will be met if one Strongly ordered
|
||||
access is performed to the target right before executing the WFI.
|
||||
In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
|
||||
IO barrier ensure that there is no synchronisation loss on initiators
|
||||
operating on both interconnect port simultaneously.
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -30,5 +30,4 @@ int __weak omap_secure_ram_reserve_memblock(void)
|
|||
void __init omap_reserve(void)
|
||||
{
|
||||
omap_secure_ram_reserve_memblock();
|
||||
omap_barrier_reserve_memblock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -200,9 +200,6 @@ void __init omap4_map_io(void);
|
|||
void __init omap5_map_io(void);
|
||||
void __init ti81xx_map_io(void);
|
||||
|
||||
/* omap_barriers_init() is OMAP4 only */
|
||||
void omap_barriers_init(void);
|
||||
|
||||
/**
|
||||
* omap_test_timeout - busy-loop, testing a condition
|
||||
* @cond: condition to test until it evaluates to true
|
||||
|
|
|
|||
|
|
@ -306,7 +306,6 @@ void __init am33xx_map_io(void)
|
|||
void __init omap4_map_io(void)
|
||||
{
|
||||
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
|
||||
omap_barriers_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -314,7 +313,6 @@ void __init omap4_map_io(void)
|
|||
void __init omap5_map_io(void)
|
||||
{
|
||||
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
|
||||
omap_barriers_init();
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1053,7 +1053,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition,
|
|||
struct omap_mux *entry;
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
if (!superset->muxnames || !superset->muxnames[0]) {
|
||||
if (!superset->muxnames[0]) {
|
||||
superset++;
|
||||
continue;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,13 +70,6 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
|
|||
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
|
||||
extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
|
||||
|
||||
#ifdef CONFIG_OMAP4_ERRATA_I688
|
||||
extern int omap_barrier_reserve_memblock(void);
|
||||
#else
|
||||
static inline void omap_barrier_reserve_memblock(void)
|
||||
{ }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
|
||||
void set_cntfreq(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -51,75 +51,6 @@ static void __iomem *twd_base;
|
|||
|
||||
#define IRQ_LOCALTIMER 29
|
||||
|
||||
#ifdef CONFIG_OMAP4_ERRATA_I688
|
||||
/* Used to implement memory barrier on DRAM path */
|
||||
#define OMAP4_DRAM_BARRIER_VA 0xfe600000
|
||||
|
||||
void __iomem *dram_sync, *sram_sync;
|
||||
|
||||
static phys_addr_t paddr;
|
||||
static u32 size;
|
||||
|
||||
void omap_bus_sync(void)
|
||||
{
|
||||
if (dram_sync && sram_sync) {
|
||||
writel_relaxed(readl_relaxed(dram_sync), dram_sync);
|
||||
writel_relaxed(readl_relaxed(sram_sync), sram_sync);
|
||||
isb();
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(omap_bus_sync);
|
||||
|
||||
static int __init omap4_sram_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct gen_pool *sram_pool;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
|
||||
if (!np)
|
||||
pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
|
||||
__func__);
|
||||
sram_pool = of_get_named_gen_pool(np, "sram", 0);
|
||||
if (!sram_pool)
|
||||
pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
|
||||
__func__);
|
||||
else
|
||||
sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
omap_arch_initcall(omap4_sram_init);
|
||||
|
||||
/* Steal one page physical memory for barrier implementation */
|
||||
int __init omap_barrier_reserve_memblock(void)
|
||||
{
|
||||
|
||||
size = ALIGN(PAGE_SIZE, SZ_1M);
|
||||
paddr = arm_memblock_steal(size, SZ_1M);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init omap_barriers_init(void)
|
||||
{
|
||||
struct map_desc dram_io_desc[1];
|
||||
|
||||
dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
|
||||
dram_io_desc[0].pfn = __phys_to_pfn(paddr);
|
||||
dram_io_desc[0].length = size;
|
||||
dram_io_desc[0].type = MT_MEMORY_RW_SO;
|
||||
iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
|
||||
dram_sync = (void __iomem *) dram_io_desc[0].virtual;
|
||||
|
||||
pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
|
||||
(long long) paddr, dram_io_desc[0].virtual);
|
||||
|
||||
}
|
||||
#else
|
||||
void __init omap_barriers_init(void)
|
||||
{}
|
||||
#endif
|
||||
|
||||
void gic_dist_disable(void)
|
||||
{
|
||||
if (gic_dist_base_addr)
|
||||
|
|
|
|||
|
|
@ -333,11 +333,9 @@ ENDPROC(omap4_cpu_resume)
|
|||
|
||||
#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
|
||||
|
||||
#ifndef CONFIG_OMAP4_ERRATA_I688
|
||||
ENTRY(omap_bus_sync)
|
||||
ret lr
|
||||
ENDPROC(omap_bus_sync)
|
||||
#endif
|
||||
|
||||
ENTRY(omap_do_wfi)
|
||||
stmfd sp!, {lr}
|
||||
|
|
|
|||
|
|
@ -39,14 +39,14 @@ config CPU_S3C2412
|
|||
bool "SAMSUNG S3C2412"
|
||||
select CPU_ARM926T
|
||||
select S3C2412_COMMON_CLK
|
||||
select S3C2412_PM if PM
|
||||
select S3C2412_PM if PM_SLEEP
|
||||
help
|
||||
Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
|
||||
|
||||
config CPU_S3C2416
|
||||
bool "SAMSUNG S3C2416/S3C2450"
|
||||
select CPU_ARM926T
|
||||
select S3C2416_PM if PM
|
||||
select S3C2416_PM if PM_SLEEP
|
||||
select S3C2443_COMMON_CLK
|
||||
help
|
||||
Support for the S3C2416 SoC from the S3C24XX line
|
||||
|
|
@ -55,7 +55,7 @@ config CPU_S3C2440
|
|||
bool "SAMSUNG S3C2440"
|
||||
select CPU_ARM920T
|
||||
select S3C2410_COMMON_CLK
|
||||
select S3C2410_PM if PM
|
||||
select S3C2410_PM if PM_SLEEP
|
||||
help
|
||||
Support for S3C2440 Samsung Mobile CPU based systems.
|
||||
|
||||
|
|
@ -63,7 +63,7 @@ config CPU_S3C2442
|
|||
bool "SAMSUNG S3C2442"
|
||||
select CPU_ARM920T
|
||||
select S3C2410_COMMON_CLK
|
||||
select S3C2410_PM if PM
|
||||
select S3C2410_PM if PM_SLEEP
|
||||
help
|
||||
Support for S3C2442 Samsung Mobile CPU based systems.
|
||||
|
||||
|
|
@ -228,11 +228,6 @@ config H1940BT
|
|||
This is a simple driver that is able to control
|
||||
the state of built in bluetooth chip on h1940.
|
||||
|
||||
config PM_H1940
|
||||
bool
|
||||
help
|
||||
Internal node for H1940 and related PM
|
||||
|
||||
config MACH_N30
|
||||
bool "Acer N30 family"
|
||||
select S3C_DEV_NAND
|
||||
|
|
@ -362,6 +357,7 @@ if CPU_S3C2416
|
|||
config S3C2416_PM
|
||||
bool
|
||||
select S3C2412_PM_SLEEP
|
||||
select SAMSUNG_WAKEMASK
|
||||
help
|
||||
Internal config node to apply S3C2416 power management
|
||||
|
||||
|
|
@ -584,6 +580,11 @@ config MACH_SMDK2443
|
|||
|
||||
endif # CPU_S3C2443
|
||||
|
||||
config PM_H1940
|
||||
bool
|
||||
help
|
||||
Internal node for H1940 and related PM
|
||||
|
||||
endmenu # SAMSUNG S3C24XX SoCs Support
|
||||
|
||||
endif # ARCH_S3C24XX
|
||||
|
|
|
|||
|
|
@ -32,7 +32,8 @@ obj-$(CONFIG_CPU_S3C2443) += s3c2443.o
|
|||
|
||||
# PM
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM_SLEEP) += irq-pm.o sleep.o
|
||||
|
||||
# common code
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,11 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "regs-clock.h"
|
||||
#include "regs-irq.h"
|
||||
|
||||
static inline void s3c_pm_debug_init_uart(void)
|
||||
{
|
||||
|
|
@ -42,8 +47,23 @@ static inline void s3c_pm_arch_stop_clocks(void)
|
|||
__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
|
||||
}
|
||||
|
||||
static void s3c_pm_show_resume_irqs(int start, unsigned long which,
|
||||
unsigned long mask);
|
||||
/* s3c2410_pm_show_resume_irqs
|
||||
*
|
||||
* print any IRQs asserted at resume time (ie, we woke from)
|
||||
*/
|
||||
static inline void s3c_pm_show_resume_irqs(int start, unsigned long which,
|
||||
unsigned long mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
which &= ~mask;
|
||||
|
||||
for (i = 0; i <= 31; i++) {
|
||||
if (which & (1L<<i)) {
|
||||
S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_show_resume_irqs(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include "s3c2412-power.h"
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
extern void s3c2412_sleep_enter(void);
|
||||
|
||||
static int s3c2416_cpu_suspend(unsigned long arg)
|
||||
|
|
@ -70,7 +71,7 @@ static __init int s3c2416_pm_init(void)
|
|||
}
|
||||
|
||||
arch_initcall(s3c2416_pm_init);
|
||||
|
||||
#endif
|
||||
|
||||
static void s3c2416_pm_resume(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@
|
|||
|
||||
#define PFX "s3c24xx-pm: "
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save core_save[] = {
|
||||
/* we restore the timings here, with the proviso that the board
|
||||
* brings the system up in an slower, or equal frequency setting
|
||||
|
|
@ -67,6 +68,7 @@ static struct sleep_save core_save[] = {
|
|||
SAVE_ITEM(S3C2410_BANKCON4),
|
||||
SAVE_ITEM(S3C2410_BANKCON5),
|
||||
};
|
||||
#endif
|
||||
|
||||
/* s3c_pm_check_resume_pin
|
||||
*
|
||||
|
|
@ -121,7 +123,7 @@ void s3c_pm_configure_extint(void)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
void s3c_pm_restore_core(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
|
||||
|
|
@ -131,4 +133,4 @@ void s3c_pm_save_core(void)
|
|||
{
|
||||
s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ int __init s3c2410_init(void)
|
|||
{
|
||||
printk("S3C2410: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -172,7 +172,7 @@ int __init s3c2412_init(void)
|
|||
{
|
||||
printk("S3C2412: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&s3c2412_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ int __init s3c2416_init(void)
|
|||
s3c_adc_setname("s3c2416-adc");
|
||||
s3c_rtc_setname("s3c2416-rtc");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&s3c2416_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
register_syscore_ops(&s3c2416_irq_syscore_ops);
|
||||
|
|
|
|||
|
|
@ -57,11 +57,11 @@ int __init s3c2440_init(void)
|
|||
|
||||
/* register suspend/resume handlers */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
#endif
|
||||
|
||||
/* register our system device for everything else */
|
||||
|
||||
|
|
|
|||
|
|
@ -60,11 +60,11 @@ int __init s3c2442_init(void)
|
|||
{
|
||||
printk("S3C2442: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
#endif
|
||||
|
||||
return device_register(&s3c2442_dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ static int __init s3c2442_core_init(void)
|
|||
core_initcall(s3c2442_core_init);
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save s3c244x_sleep[] = {
|
||||
SAVE_ITEM(S3C2440_DSC0),
|
||||
SAVE_ITEM(S3C2440_DSC1),
|
||||
|
|
@ -127,12 +127,9 @@ static void s3c244x_resume(void)
|
|||
{
|
||||
s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
|
||||
}
|
||||
#else
|
||||
#define s3c244x_suspend NULL
|
||||
#define s3c244x_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops s3c244x_pm_syscore_ops = {
|
||||
.suspend = s3c244x_suspend,
|
||||
.resume = s3c244x_resume,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -189,6 +189,7 @@ endchoice
|
|||
config SMDK6410_WM1190_EV1
|
||||
bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
|
||||
depends on MACH_SMDK6410
|
||||
depends on I2C=y
|
||||
select MFD_WM8350_I2C
|
||||
select REGULATOR
|
||||
select REGULATOR_WM8350
|
||||
|
|
@ -203,6 +204,7 @@ config SMDK6410_WM1190_EV1
|
|||
config SMDK6410_WM1192_EV1
|
||||
bool "Support Wolfson Microelectronics 1192-EV1 PMIC card"
|
||||
depends on MACH_SMDK6410
|
||||
depends on I2C=y
|
||||
select MFD_WM831X
|
||||
select MFD_WM831X_I2C
|
||||
select REGULATOR
|
||||
|
|
@ -269,8 +271,8 @@ config MACH_SMARTQ7
|
|||
|
||||
config MACH_WLF_CRAGG_6410
|
||||
bool "Wolfson Cragganmore 6410"
|
||||
depends on I2C=y
|
||||
select CPU_S3C6410
|
||||
select I2C
|
||||
select LEDS_GPIO_REGISTER
|
||||
select S3C64XX_DEV_SPI0
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
|
|||
|
||||
# PM
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM_SLEEP) += irq-pm.o sleep.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
|
||||
# DMA support
|
||||
|
|
|
|||
|
|
@ -209,7 +209,7 @@ static struct platform_device smdk6410_smsc911x = {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = {
|
||||
static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
|
||||
REGULATOR_SUPPLY("PVDD", "0-001b"),
|
||||
REGULATOR_SUPPLY("AVDD", "0-001b"),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -194,6 +194,7 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save core_save[] = {
|
||||
SAVE_ITEM(S3C64XX_MEM0DRVCON),
|
||||
SAVE_ITEM(S3C64XX_MEM1DRVCON),
|
||||
|
|
@ -238,6 +239,7 @@ void s3c_pm_save_core(void)
|
|||
s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
|
||||
s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
|
||||
}
|
||||
#endif
|
||||
|
||||
/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
|
||||
* put the per-cpu code in here until any new cpu comes along and changes
|
||||
|
|
|
|||
|
|
@ -43,7 +43,11 @@ extern unsigned long s3c_irqwake_eintmask;
|
|||
|
||||
/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
|
||||
extern unsigned long s3c_irqwake_intallow;
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
extern unsigned long s3c_irqwake_eintallow;
|
||||
#else
|
||||
#define s3c_irqwake_eintallow 0
|
||||
#endif
|
||||
|
||||
/* per-cpu sleep functions */
|
||||
|
||||
|
|
@ -58,16 +62,20 @@ extern unsigned long s3c_pm_flags;
|
|||
|
||||
extern int s3c2410_cpu_suspend(unsigned long);
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_PM
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
|
||||
extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
|
||||
extern void s3c_cpu_resume(void);
|
||||
#else
|
||||
#define s3c_irq_wake NULL
|
||||
#define s3c_irqext_wake NULL
|
||||
#define s3c_cpu_resume NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_PM
|
||||
extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
|
||||
#else
|
||||
#define s3c_irqext_wake NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
|
||||
/**
|
||||
* s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <plat/pm-common.h>
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_ATAGS
|
||||
#include <plat/pm.h>
|
||||
#include <mach/pm-core.h>
|
||||
#else
|
||||
static inline void s3c_pm_debug_init_uart(void) {}
|
||||
|
|
|
|||
|
|
@ -65,26 +65,6 @@ int s3c_irqext_wake(struct irq_data *data, unsigned int state)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* s3c2410_pm_show_resume_irqs
|
||||
*
|
||||
* print any IRQs asserted at resume time (ie, we woke from)
|
||||
*/
|
||||
static void __maybe_unused s3c_pm_show_resume_irqs(int start,
|
||||
unsigned long which,
|
||||
unsigned long mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
which &= ~mask;
|
||||
|
||||
for (i = 0; i <= 31; i++) {
|
||||
if (which & (1L<<i)) {
|
||||
S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void (*pm_cpu_prep)(void);
|
||||
int (*pm_cpu_sleep)(unsigned long);
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -23,6 +24,9 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#define OCP2SCP_TIMING 0x18
|
||||
#define SYNC2_MASK 0xf
|
||||
|
||||
static int ocp2scp_remove_devices(struct device *dev, void *c)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
|
|
@ -35,6 +39,9 @@ static int ocp2scp_remove_devices(struct device *dev, void *c)
|
|||
static int omap_ocp2scp_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
u32 reg;
|
||||
void __iomem *regs;
|
||||
struct resource *res;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
if (np) {
|
||||
|
|
@ -47,6 +54,32 @@ static int omap_ocp2scp_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
/*
|
||||
* As per AM572x TRM: http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf
|
||||
* under section 26.3.2.2, table 26-26 OCP2SCP TIMING Caution;
|
||||
* As per OMAP4430 TRM: http://www.ti.com/lit/ug/swpu231ap/swpu231ap.pdf
|
||||
* under section 23.12.6.2.2 , Table 23-1213 OCP2SCP TIMING Caution;
|
||||
* As per OMAP4460 TRM: http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf
|
||||
* under section 23.12.6.2.2, Table 23-1213 OCP2SCP TIMING Caution;
|
||||
* As per OMAP543x TRM http://www.ti.com/lit/pdf/swpu249
|
||||
* under section 27.3.2.2, Table 27-27 OCP2SCP TIMING Caution;
|
||||
*
|
||||
* Read path of OCP2SCP is not working properly due to low reset value
|
||||
* of SYNC2 parameter in OCP2SCP. Suggested reset value is 0x6 or more.
|
||||
*/
|
||||
if (!of_device_is_compatible(np, "ti,am437x-ocp2scp")) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(regs))
|
||||
goto err0;
|
||||
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
reg = readl_relaxed(regs + OCP2SCP_TIMING);
|
||||
reg &= ~(SYNC2_MASK);
|
||||
reg |= 0x6;
|
||||
writel_relaxed(reg, regs + OCP2SCP_TIMING);
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -67,6 +100,7 @@ static int omap_ocp2scp_remove(struct platform_device *pdev)
|
|||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id omap_ocp2scp_id_table[] = {
|
||||
{ .compatible = "ti,omap-ocp2scp" },
|
||||
{ .compatible = "ti,am437x-ocp2scp" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, omap_ocp2scp_id_table);
|
||||
|
|
|
|||
|
|
@ -116,7 +116,8 @@ static int exynos_cpuidle_probe(struct platform_device *pdev)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (of_machine_is_compatible("samsung,exynos4210")) {
|
||||
if (IS_ENABLED(CONFIG_SMP) &&
|
||||
of_machine_is_compatible("samsung,exynos4210")) {
|
||||
exynos_cpuidle_pdata = pdev->dev.platform_data;
|
||||
|
||||
ret = cpuidle_register(&exynos_coupled_idle_driver,
|
||||
|
|
|
|||
|
|
@ -282,7 +282,8 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
|
|||
$(call cmd,dt_S_dtb)
|
||||
|
||||
quiet_cmd_dtc = DTC $@
|
||||
cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
|
||||
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
|
||||
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
|
||||
$(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
|
||||
-i $(dir $<) $(DTC_FLAGS) \
|
||||
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
|
||||
|
|
|
|||
Loading…
Reference in New Issue