Merge tag 'drm-msm-next-2023-08-20' of https://gitlab.freedesktop.org/drm/msm into drm-next
Updates for v6.6, which includes a backmerge of msm-fixes to avoid conficts. Core: - SM6125 MDSS support DPU: - SM6125 DPU support - Added subblocks to display snapshot - Use UBWC data from MDSS driver rather than duplicating it - dpu_core_perf cleanup DSI: - Enabled burst mode to fix CMD mode panels - Runtime PM support - refgen regulator support DSI PHY: - SM6125 support in 14nm DSI PHY driver GPU: - Rework GPU identification to prepare for a7xx, and other a7xx prep - Cleanups and fixes - Disallow legacy relocs on a6xx and newer - a690: switch to using a660_gmu.bin fw as this is what we have in linux-firmware and we see no evidence that it should be different from other a660 family (a6xx subgen 4) devices - Submit overhead opts, 1.6x faster for NO_IMPLICIT_SYNC commits with 100 BOs to 2.5x faster for 1000 BOs Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGv_01g-edjdfKLWWcb-rO5aSyLsv5FpbKrTkXVL9+ngTQ@mail.gmail.com
This commit is contained in:
commit
38f88732b2
|
@ -29,6 +29,7 @@ properties:
|
|||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
- description: AHB config clock from GCC
|
||||
- description: GPLL0 div source from GCC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
|
@ -39,6 +40,7 @@ properties:
|
|||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
- const: cfg_ahb_clk
|
||||
- const: gcc_disp_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
@ -46,6 +48,16 @@ properties:
|
|||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the CX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing the power domain's performance point.
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
@ -63,23 +75,31 @@ examples:
|
|||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@5f00000 {
|
||||
compatible = "qcom,sm6125-dispcc";
|
||||
reg = <0x5f00000 0x20000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>,
|
||||
<&gcc GCC_DISP_AHB_CLK>;
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dsi1_phy_pll_out_dsiclk",
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk",
|
||||
"cfg_ahb_clk";
|
||||
"cfg_ahb_clk",
|
||||
"gcc_disp_gpll0_div_clk_src";
|
||||
|
||||
required-opps = <&rpmhpd_opp_ret>;
|
||||
power-domains = <&rpmpd SM6125_VDDCX>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
|
|
@ -28,6 +28,7 @@ properties:
|
|||
- qcom,sm8350-dp
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8250-dp
|
||||
- qcom,sm8450-dp
|
||||
- qcom,sm8550-dp
|
||||
- const: qcom,sm8350-dp
|
||||
|
|
|
@ -27,6 +27,7 @@ properties:
|
|||
- qcom,sdm660-dsi-ctrl
|
||||
- qcom,sdm845-dsi-ctrl
|
||||
- qcom,sm6115-dsi-ctrl
|
||||
- qcom,sm6125-dsi-ctrl
|
||||
- qcom,sm6350-dsi-ctrl
|
||||
- qcom,sm6375-dsi-ctrl
|
||||
- qcom,sm8150-dsi-ctrl
|
||||
|
@ -166,6 +167,10 @@ properties:
|
|||
description:
|
||||
Phandle to vdd regulator device node
|
||||
|
||||
refgen-supply:
|
||||
description:
|
||||
Phandle to REFGEN regulator device node
|
||||
|
||||
vcca-supply:
|
||||
description:
|
||||
Phandle to vdd regulator device node
|
||||
|
@ -301,6 +306,7 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- qcom,msm8998-dsi-ctrl
|
||||
- qcom,sm6125-dsi-ctrl
|
||||
- qcom,sm6350-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
|
|
|
@ -19,6 +19,7 @@ properties:
|
|||
- qcom,dsi-phy-14nm-2290
|
||||
- qcom,dsi-phy-14nm-660
|
||||
- qcom,dsi-phy-14nm-8953
|
||||
- qcom,sm6125-dsi-phy-14nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
@ -35,6 +36,16 @@ properties:
|
|||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for an optional power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing the power domain's performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
@ -13,6 +13,12 @@ maintainers:
|
|||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: |
|
||||
The driver is parsing the compat string for Adreno to
|
||||
figure out the chip-id.
|
||||
items:
|
||||
- pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
|
||||
- const: qcom,adreno
|
||||
- description: |
|
||||
The driver is parsing the compat string for Adreno to
|
||||
figure out the gpu-id and patch level.
|
||||
|
|
|
@ -77,6 +77,12 @@ properties:
|
|||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to a node describing a reserved framebuffer memory region.
|
||||
For example, the splash memory region set up by the bootloader.
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
|
|
|
@ -15,6 +15,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-dpu
|
||||
- qcom,sm6125-dpu
|
||||
- qcom,sm6350-dpu
|
||||
- qcom,sm6375-dpu
|
||||
|
||||
|
@ -63,7 +64,9 @@ allOf:
|
|||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6375-dpu
|
||||
enum:
|
||||
- qcom,sm6375-dpu
|
||||
- qcom,sm6125-dpu
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
|
|
@ -0,0 +1,213 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM6125 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Marijn Suijten <marijn.suijten@somainline.org>
|
||||
|
||||
description:
|
||||
SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
|
||||
like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6125-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6125-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6125-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6125-dsi-phy-14nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@5e00000 {
|
||||
compatible = "qcom,sm6125-mdss";
|
||||
reg = <0x05e00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface",
|
||||
"ahb",
|
||||
"core";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
iommus = <&apps_smmu 0x400 0x0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@5e01000 {
|
||||
compatible = "qcom,sm6125-dpu";
|
||||
reg = <0x05e01000 0x83208>,
|
||||
<0x05eb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&gcc GCC_DISP_THROTTLE_CORE_CLK>;
|
||||
clock-names = "bus",
|
||||
"iface",
|
||||
"rot",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync",
|
||||
"throttle";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd SM6125_VDDCX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@5e94000 {
|
||||
compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x05e94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmpd SM6125_VDDCX>;
|
||||
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
phy@5e94400 {
|
||||
compatible = "qcom,sm6125-dsi-phy-14nm";
|
||||
reg = <0x05e94400 0x100>,
|
||||
<0x05e94500 0x300>,
|
||||
<0x05e94800 0x188>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface",
|
||||
"ref";
|
||||
|
||||
required-opps = <&rpmpd_opp_nom>;
|
||||
power-domains = <&rpmpd SM6125_VDDMX>;
|
||||
};
|
||||
};
|
||||
...
|
|
@ -131,13 +131,6 @@ examples:
|
|||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -132,13 +132,6 @@ examples:
|
|||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -52,6 +52,12 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,sm8350-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8350-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
|
|
|
@ -42,6 +42,14 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,sm8450-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8450-dp
|
||||
- const: qcom,sm8350-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
|
|
|
@ -42,6 +42,14 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,sm8550-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8550-dp
|
||||
- const: qcom,sm8350-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
|
|
|
@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
|
|||
A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);
|
||||
|
||||
for (i = 3; i <= 5; i++)
|
||||
if ((SZ_16K << i) == adreno_gpu->gmem)
|
||||
if ((SZ_16K << i) == adreno_gpu->info->gmem)
|
||||
break;
|
||||
gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);
|
||||
|
||||
|
@ -540,6 +540,10 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
|
|||
gpu->perfcntrs = perfcntrs;
|
||||
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
|
||||
|
||||
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
if (adreno_is_a20x(adreno_gpu))
|
||||
adreno_gpu->registers = a200_registers;
|
||||
else if (adreno_is_a225(adreno_gpu))
|
||||
|
@ -547,10 +551,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
|
|||
else
|
||||
adreno_gpu->registers = a220_registers;
|
||||
|
||||
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
if (!gpu->aspace) {
|
||||
dev_err(dev->dev, "No memory protection without MMU\n");
|
||||
if (!allow_vram_carveout) {
|
||||
|
|
|
@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
|
|||
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
|
||||
/* Early A430's have a timing issue with SP/TP power collapse;
|
||||
disabling HW clock gating prevents it. */
|
||||
if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
|
||||
if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
|
||||
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
|
||||
else
|
||||
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
|
||||
|
|
|
@ -66,7 +66,7 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
|
|||
static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
||||
{
|
||||
struct msm_ringbuffer *ring = submit->ring;
|
||||
struct msm_gem_object *obj;
|
||||
struct drm_gem_object *obj;
|
||||
uint32_t *ptr, dwords;
|
||||
unsigned int i;
|
||||
|
||||
|
@ -83,7 +83,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit
|
|||
obj = submit->bos[submit->cmd[i].idx].obj;
|
||||
dwords = submit->cmd[i].size;
|
||||
|
||||
ptr = msm_gem_get_vaddr(&obj->base);
|
||||
ptr = msm_gem_get_vaddr(obj);
|
||||
|
||||
/* _get_vaddr() shouldn't fail at this point,
|
||||
* since we've already mapped it once in
|
||||
|
@ -103,7 +103,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit
|
|||
OUT_RING(ring, ptr[i]);
|
||||
}
|
||||
|
||||
msm_gem_put_vaddr(&obj->base);
|
||||
msm_gem_put_vaddr(obj);
|
||||
|
||||
break;
|
||||
}
|
||||
|
@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
|
|||
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
|
||||
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
|
||||
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
|
||||
0x00100000 + adreno_gpu->gmem - 1);
|
||||
0x00100000 + adreno_gpu->info->gmem - 1);
|
||||
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
|
||||
|
||||
if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
|
||||
|
@ -1770,7 +1770,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
|
|||
|
||||
nr_rings = 4;
|
||||
|
||||
if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
|
||||
if (config->info->revn == 510)
|
||||
nr_rings = 1;
|
||||
|
||||
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
|
||||
|
|
|
@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
|
|||
|
||||
/* The battery current limiter isn't enabled for A540 */
|
||||
config = AGC_LM_CONFIG_BCL_DISABLED;
|
||||
config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
|
||||
config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
|
||||
|
||||
/* For now disable GPMU side throttling */
|
||||
config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
|
||||
|
|
|
@ -1166,6 +1166,9 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
|
|||
#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
|
||||
|
||||
#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
|
||||
#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008
|
||||
#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002
|
||||
#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001
|
||||
|
||||
static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
|
||||
|
||||
|
|
|
@ -792,10 +792,22 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
|
|||
gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
|
||||
(1 << 31) | (0xa << 18) | (0xa0));
|
||||
|
||||
chipid = adreno_gpu->rev.core << 24;
|
||||
chipid |= adreno_gpu->rev.major << 16;
|
||||
chipid |= adreno_gpu->rev.minor << 12;
|
||||
chipid |= adreno_gpu->rev.patchid << 8;
|
||||
/*
|
||||
* Snapshots toggle the NMI bit which will result in a jump to the NMI
|
||||
* handler instead of __main. Set the M3 config value to avoid that.
|
||||
*/
|
||||
gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
|
||||
|
||||
/*
|
||||
* Note that the GMU has a slightly different layout for
|
||||
* chip_id, for whatever reason, so a bit of massaging
|
||||
* is needed. The upper 16b are the same, but minor and
|
||||
* patchid are packed in four bits each with the lower
|
||||
* 8b unused:
|
||||
*/
|
||||
chipid = adreno_gpu->chip_id & 0xffff0000;
|
||||
chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
|
||||
chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
|
||||
|
||||
gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
|
||||
|
||||
|
@ -889,6 +901,13 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
|
|||
/* Make sure there are no outstanding RPMh votes */
|
||||
a6xx_gmu_rpmh_off(gmu);
|
||||
|
||||
/* Clear the WRITEDROPPED fields and put fence into allow mode */
|
||||
gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
|
||||
gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
|
||||
|
||||
/* Make sure the above writes go through */
|
||||
wmb();
|
||||
|
||||
/* Halt the gmu cm3 core */
|
||||
gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
|
||||
|
||||
|
@ -1437,8 +1456,15 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
|
|||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
struct platform_device *pdev = to_platform_device(gmu->dev);
|
||||
|
||||
if (!gmu->initialized)
|
||||
mutex_lock(&gmu->lock);
|
||||
if (!gmu->initialized) {
|
||||
mutex_unlock(&gmu->lock);
|
||||
return;
|
||||
}
|
||||
|
||||
gmu->initialized = false;
|
||||
|
||||
mutex_unlock(&gmu->lock);
|
||||
|
||||
pm_runtime_force_suspend(gmu->dev);
|
||||
|
||||
|
@ -1468,8 +1494,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
|
|||
|
||||
/* Drop reference taken in of_find_device_by_node */
|
||||
put_device(gmu->dev);
|
||||
|
||||
gmu->initialized = false;
|
||||
}
|
||||
|
||||
static int cxpd_notifier_cb(struct notifier_block *nb,
|
||||
|
@ -1619,7 +1643,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
|
|||
SZ_256K - SZ_16K, 0x44000, "dcache");
|
||||
if (ret)
|
||||
goto err_memory;
|
||||
} else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) {
|
||||
} else if (adreno_is_a630_family(adreno_gpu)) {
|
||||
/* HFI v1, has sptprac */
|
||||
gmu->legacy = true;
|
||||
|
||||
|
@ -1629,13 +1653,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
|
|||
goto err_memory;
|
||||
}
|
||||
|
||||
/* Allocate memory for for the HFI queues */
|
||||
ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
|
||||
/* Allocate memory for the GMU log region */
|
||||
ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log");
|
||||
if (ret)
|
||||
goto err_memory;
|
||||
|
||||
/* Allocate memory for the GMU log region */
|
||||
ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log");
|
||||
/* Allocate memory for for the HFI queues */
|
||||
ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
|
||||
if (ret)
|
||||
goto err_memory;
|
||||
|
||||
|
|
|
@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
|
|||
|
||||
#define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313
|
||||
|
||||
#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314
|
||||
|
||||
#define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315
|
||||
|
||||
#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
|
||||
|
|
|
@ -930,10 +930,16 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
|
|||
* protect violation and select the last span to protect from the start
|
||||
* address all the way to the end of the register address space
|
||||
*/
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL,
|
||||
A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN |
|
||||
A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN |
|
||||
A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE);
|
||||
|
||||
for (i = 0; i < count - 1; i++)
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
|
||||
for (i = 0; i < count - 1; i++) {
|
||||
/* Intentionally skip writing to some registers */
|
||||
if (regs[i])
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
|
||||
}
|
||||
/* last CP_PROTECT to have "infinite" length on the last entry */
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
|
||||
}
|
||||
|
@ -1195,7 +1201,9 @@ static int hw_init(struct msm_gpu *gpu)
|
|||
|
||||
if (!adreno_has_gmu_wrapper(adreno_gpu)) {
|
||||
/* Make sure the GMU keeps the GPU on while we set it up */
|
||||
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
|
||||
ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Clear GBIF halt in case GX domain was not collapsed */
|
||||
|
@ -1270,7 +1278,7 @@ static int hw_init(struct msm_gpu *gpu)
|
|||
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
|
||||
|
||||
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX,
|
||||
0x00100000 + adreno_gpu->gmem - 1);
|
||||
0x00100000 + adreno_gpu->info->gmem - 1);
|
||||
}
|
||||
|
||||
gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
|
||||
|
@ -1729,16 +1737,6 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
|
||||
{
|
||||
return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
|
||||
}
|
||||
|
||||
static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
|
||||
{
|
||||
msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
|
||||
}
|
||||
|
||||
static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
|
||||
{
|
||||
llcc_slice_deactivate(a6xx_gpu->llc_slice);
|
||||
|
@ -2091,9 +2089,7 @@ static void a6xx_destroy(struct msm_gpu *gpu)
|
|||
|
||||
a6xx_llc_slices_destroy(a6xx_gpu);
|
||||
|
||||
mutex_lock(&a6xx_gpu->gmu.lock);
|
||||
a6xx_gmu_remove(a6xx_gpu);
|
||||
mutex_unlock(&a6xx_gpu->gmu.lock);
|
||||
|
||||
adreno_gpu_cleanup(adreno_gpu);
|
||||
|
||||
|
@ -2204,159 +2200,19 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
|
|||
return progress;
|
||||
}
|
||||
|
||||
static u32 a610_get_speed_bin(u32 fuse)
|
||||
static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
|
||||
{
|
||||
/*
|
||||
* There are (at least) three SoCs implementing A610: SM6125 (trinket),
|
||||
* SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning,
|
||||
* as only a single SKU exists and we don't support khaje upstream yet.
|
||||
* Hence, this matching table is only valid for bengal and can be easily
|
||||
* expanded if need be.
|
||||
*/
|
||||
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
else if (fuse == 206)
|
||||
return 1;
|
||||
else if (fuse == 200)
|
||||
return 2;
|
||||
else if (fuse == 157)
|
||||
return 3;
|
||||
else if (fuse == 127)
|
||||
return 4;
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 a618_get_speed_bin(u32 fuse)
|
||||
{
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
else if (fuse == 169)
|
||||
return 1;
|
||||
else if (fuse == 174)
|
||||
return 2;
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 a619_holi_get_speed_bin(u32 fuse)
|
||||
{
|
||||
/*
|
||||
* There are (at least) two SoCs implementing A619_holi: SM4350 (holi)
|
||||
* and SM6375 (blair). Limit the fuse matching to the corresponding
|
||||
* SoC to prevent bogus frequency setting (as improbable as it may be,
|
||||
* given unexpected fuse values are.. unexpected! But still possible.)
|
||||
*/
|
||||
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
|
||||
if (of_machine_is_compatible("qcom,sm4350")) {
|
||||
if (fuse == 138)
|
||||
return 1;
|
||||
else if (fuse == 92)
|
||||
return 2;
|
||||
} else if (of_machine_is_compatible("qcom,sm6375")) {
|
||||
if (fuse == 190)
|
||||
return 1;
|
||||
else if (fuse == 177)
|
||||
return 2;
|
||||
} else
|
||||
pr_warn("Unknown SoC implementing A619_holi!\n");
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 a619_get_speed_bin(u32 fuse)
|
||||
{
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
else if (fuse == 120)
|
||||
return 4;
|
||||
else if (fuse == 138)
|
||||
return 3;
|
||||
else if (fuse == 169)
|
||||
return 2;
|
||||
else if (fuse == 180)
|
||||
return 1;
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 a640_get_speed_bin(u32 fuse)
|
||||
{
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
else if (fuse == 1)
|
||||
return 1;
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 a650_get_speed_bin(u32 fuse)
|
||||
{
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
else if (fuse == 1)
|
||||
return 1;
|
||||
/* Yep, 2 and 3 are swapped! :/ */
|
||||
else if (fuse == 2)
|
||||
return 3;
|
||||
else if (fuse == 3)
|
||||
return 2;
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 adreno_7c3_get_speed_bin(u32 fuse)
|
||||
{
|
||||
if (fuse == 0)
|
||||
return 0;
|
||||
else if (fuse == 117)
|
||||
return 0;
|
||||
else if (fuse == 190)
|
||||
return 1;
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse)
|
||||
{
|
||||
u32 val = UINT_MAX;
|
||||
|
||||
if (adreno_is_a610(adreno_gpu))
|
||||
val = a610_get_speed_bin(fuse);
|
||||
|
||||
if (adreno_is_a618(adreno_gpu))
|
||||
val = a618_get_speed_bin(fuse);
|
||||
|
||||
else if (adreno_is_a619_holi(adreno_gpu))
|
||||
val = a619_holi_get_speed_bin(fuse);
|
||||
|
||||
else if (adreno_is_a619(adreno_gpu))
|
||||
val = a619_get_speed_bin(fuse);
|
||||
|
||||
else if (adreno_is_7c3(adreno_gpu))
|
||||
val = adreno_7c3_get_speed_bin(fuse);
|
||||
|
||||
else if (adreno_is_a640(adreno_gpu))
|
||||
val = a640_get_speed_bin(fuse);
|
||||
|
||||
else if (adreno_is_a650(adreno_gpu))
|
||||
val = a650_get_speed_bin(fuse);
|
||||
|
||||
if (val == UINT_MAX) {
|
||||
DRM_DEV_ERROR(dev,
|
||||
"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
|
||||
fuse);
|
||||
if (!info->speedbins)
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
return (1 << val);
|
||||
for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++)
|
||||
if (info->speedbins[i].fuse == fuse)
|
||||
return BIT(info->speedbins[i].speedbin);
|
||||
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu)
|
||||
static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
|
||||
{
|
||||
u32 supp_hw;
|
||||
u32 speedbin;
|
||||
|
@ -2375,7 +2231,14 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_g
|
|||
return ret;
|
||||
}
|
||||
|
||||
supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin);
|
||||
supp_hw = fuse_to_supp_hw(info, speedbin);
|
||||
|
||||
if (supp_hw == UINT_MAX) {
|
||||
DRM_DEV_ERROR(dev,
|
||||
"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
|
||||
speedbin);
|
||||
return UINT_MAX;
|
||||
}
|
||||
|
||||
ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
|
||||
if (ret)
|
||||
|
@ -2449,7 +2312,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
|||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct platform_device *pdev = priv->gpu_pdev;
|
||||
struct adreno_platform_config *config = pdev->dev.platform_data;
|
||||
const struct adreno_info *info;
|
||||
struct device_node *node;
|
||||
struct a6xx_gpu *a6xx_gpu;
|
||||
struct adreno_gpu *adreno_gpu;
|
||||
|
@ -2474,29 +2336,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
|||
|
||||
adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
|
||||
|
||||
/*
|
||||
* We need to know the platform type before calling into adreno_gpu_init
|
||||
* so that the hw_apriv flag can be correctly set. Snoop into the info
|
||||
* and grab the revision number
|
||||
*/
|
||||
info = adreno_info(config->rev);
|
||||
if (!info)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
/* Assign these early so that we can use the is_aXYZ helpers */
|
||||
/* Numeric revision IDs (e.g. 630) */
|
||||
adreno_gpu->revn = info->revn;
|
||||
/* New-style ADRENO_REV()-only */
|
||||
adreno_gpu->rev = info->rev;
|
||||
/* Quirk data */
|
||||
adreno_gpu->info = info;
|
||||
|
||||
if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
|
||||
adreno_gpu->base.hw_apriv = true;
|
||||
adreno_gpu->base.hw_apriv =
|
||||
!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
|
||||
|
||||
a6xx_llc_slices_init(pdev, a6xx_gpu);
|
||||
|
||||
ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu);
|
||||
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
|
||||
if (ret) {
|
||||
a6xx_destroy(&(a6xx_gpu->base.base));
|
||||
return ERR_PTR(ret);
|
||||
|
|
|
@ -39,8 +39,8 @@ struct a6xx_gpu {
|
|||
|
||||
/*
|
||||
* Given a register and a count, return a value to program into
|
||||
* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
|
||||
* registers starting at _reg.
|
||||
* REG_CP_PROTECT_REG(n) - this will block both reads and writes for
|
||||
* _len + 1 registers starting at _reg.
|
||||
*/
|
||||
#define A6XX_PROTECT_NORDWR(_reg, _len) \
|
||||
((1 << 31) | \
|
||||
|
@ -62,6 +62,21 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
|
|||
return true;
|
||||
}
|
||||
|
||||
static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
|
||||
{
|
||||
return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
|
||||
}
|
||||
|
||||
static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
|
||||
{
|
||||
return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
|
||||
}
|
||||
|
||||
static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
|
||||
{
|
||||
msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
|
||||
}
|
||||
|
||||
#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
|
||||
((_ring)->id * sizeof(uint32_t)))
|
||||
|
||||
|
|
|
@ -22,9 +22,9 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
|
|||
|
||||
static const struct adreno_info gpulist[] = {
|
||||
{
|
||||
.rev = ADRENO_REV(2, 0, 0, 0),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x02000000),
|
||||
.family = ADRENO_2XX_GEN1,
|
||||
.revn = 200,
|
||||
.name = "A200",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "yamato_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "yamato_pfp.fw",
|
||||
|
@ -33,9 +33,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a2xx_gpu_init,
|
||||
}, { /* a200 on i.mx51 has only 128kib gmem */
|
||||
.rev = ADRENO_REV(2, 0, 0, 1),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x02000001),
|
||||
.family = ADRENO_2XX_GEN1,
|
||||
.revn = 201,
|
||||
.name = "A200",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "yamato_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "yamato_pfp.fw",
|
||||
|
@ -44,9 +44,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a2xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(2, 2, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x02020000),
|
||||
.family = ADRENO_2XX_GEN2,
|
||||
.revn = 220,
|
||||
.name = "A220",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "leia_pm4_470.fw",
|
||||
[ADRENO_FW_PFP] = "leia_pfp_470.fw",
|
||||
|
@ -55,9 +55,12 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a2xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(3, 0, 5, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(
|
||||
0x03000512,
|
||||
0x03000520
|
||||
),
|
||||
.family = ADRENO_3XX,
|
||||
.revn = 305,
|
||||
.name = "A305",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a300_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a300_pfp.fw",
|
||||
|
@ -66,9 +69,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a3xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(3, 0, 6, 0),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x03000600),
|
||||
.family = ADRENO_3XX,
|
||||
.revn = 307, /* because a305c is revn==306 */
|
||||
.name = "A306",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a300_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a300_pfp.fw",
|
||||
|
@ -77,9 +80,13 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a3xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(
|
||||
0x03020000,
|
||||
0x03020001,
|
||||
0x03020002
|
||||
),
|
||||
.family = ADRENO_3XX,
|
||||
.revn = 320,
|
||||
.name = "A320",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a300_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a300_pfp.fw",
|
||||
|
@ -88,9 +95,13 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a3xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(3, 3, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(
|
||||
0x03030000,
|
||||
0x03030001,
|
||||
0x03030002
|
||||
),
|
||||
.family = ADRENO_3XX,
|
||||
.revn = 330,
|
||||
.name = "A330",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a330_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a330_pfp.fw",
|
||||
|
@ -99,9 +110,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a3xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(4, 0, 5, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x04000500),
|
||||
.family = ADRENO_4XX,
|
||||
.revn = 405,
|
||||
.name = "A405",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a420_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a420_pfp.fw",
|
||||
|
@ -110,9 +121,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a4xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(4, 2, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x04020000),
|
||||
.family = ADRENO_4XX,
|
||||
.revn = 420,
|
||||
.name = "A420",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a420_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a420_pfp.fw",
|
||||
|
@ -121,9 +132,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a4xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(4, 3, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x04030002),
|
||||
.family = ADRENO_4XX,
|
||||
.revn = 430,
|
||||
.name = "A430",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a420_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a420_pfp.fw",
|
||||
|
@ -132,9 +143,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a4xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 0, 6, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x05000600),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 506,
|
||||
.name = "A506",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -150,9 +161,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a506_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 0, 8, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x05000800),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 508,
|
||||
.name = "A508",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -167,9 +178,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a508_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 0, 9, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x05000900),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 509,
|
||||
.name = "A509",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -185,9 +196,9 @@ static const struct adreno_info gpulist[] = {
|
|||
/* Adreno 509 uses the same ZAP as 512 */
|
||||
.zapfw = "a512_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 1, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x05010000),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 510,
|
||||
.name = "A510",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -200,9 +211,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.inactive_period = 250,
|
||||
.init = a5xx_gpu_init,
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 1, 2, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x05010200),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 512,
|
||||
.name = "A512",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -217,9 +228,12 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a512_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 3, 0, 2),
|
||||
.chip_ids = ADRENO_CHIP_IDS(
|
||||
0x05030002,
|
||||
0x05030004
|
||||
),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 530,
|
||||
.name = "A530",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -236,9 +250,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a530_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(5, 4, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x05040001),
|
||||
.family = ADRENO_5XX,
|
||||
.revn = 540,
|
||||
.name = "A540",
|
||||
.fw = {
|
||||
[ADRENO_FW_PM4] = "a530_pm4.fw",
|
||||
[ADRENO_FW_PFP] = "a530_pfp.fw",
|
||||
|
@ -254,9 +268,9 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a5xx_gpu_init,
|
||||
.zapfw = "a540_zap.mdt",
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 1, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06010000),
|
||||
.family = ADRENO_6XX_GEN1,
|
||||
.revn = 610,
|
||||
.name = "A610",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
},
|
||||
|
@ -265,21 +279,42 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a610_zap.mdt",
|
||||
.hwcg = a612_hwcg,
|
||||
/*
|
||||
* There are (at least) three SoCs implementing A610: SM6125
|
||||
* (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
|
||||
* not have speedbinning, as only a single SKU exists and we
|
||||
* don't support khaje upstream yet. Hence, this matching
|
||||
* table is only valid for bengal.
|
||||
*/
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 206, 1 },
|
||||
{ 200, 2 },
|
||||
{ 157, 3 },
|
||||
{ 127, 4 },
|
||||
),
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 1, 8, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06010800),
|
||||
.family = ADRENO_6XX_GEN1,
|
||||
.revn = 618,
|
||||
.name = "A618",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a630_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_512K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
|
||||
.init = a6xx_gpu_init,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 169, 1 },
|
||||
{ 174, 2 },
|
||||
),
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
|
||||
.machine = "qcom,sm4350",
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06010900),
|
||||
.family = ADRENO_6XX_GEN1,
|
||||
.revn = 619,
|
||||
.name = "A619",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a619_gmu.bin",
|
||||
|
@ -289,92 +324,168 @@ static const struct adreno_info gpulist[] = {
|
|||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a615_zap.mdt",
|
||||
.hwcg = a615_hwcg,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 138, 1 },
|
||||
{ 92, 2 },
|
||||
),
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 3, 0, ANY_ID),
|
||||
.machine = "qcom,sm6375",
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06010900),
|
||||
.family = ADRENO_6XX_GEN1,
|
||||
.revn = 619,
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a619_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_512K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a615_zap.mdt",
|
||||
.hwcg = a615_hwcg,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 190, 1 },
|
||||
{ 177, 2 },
|
||||
),
|
||||
}, {
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06010900),
|
||||
.family = ADRENO_6XX_GEN1,
|
||||
.revn = 619,
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a619_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_512K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a615_zap.mdt",
|
||||
.hwcg = a615_hwcg,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 120, 4 },
|
||||
{ 138, 3 },
|
||||
{ 169, 2 },
|
||||
{ 180, 1 },
|
||||
),
|
||||
}, {
|
||||
.chip_ids = ADRENO_CHIP_IDS(
|
||||
0x06030001,
|
||||
0x06030002
|
||||
),
|
||||
.family = ADRENO_6XX_GEN1,
|
||||
.revn = 630,
|
||||
.name = "A630",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a630_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_1M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a630_zap.mdt",
|
||||
.hwcg = a630_hwcg,
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 4, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
|
||||
.family = ADRENO_6XX_GEN2,
|
||||
.revn = 640,
|
||||
.name = "A640",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a640_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_1M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a640_zap.mdt",
|
||||
.hwcg = a640_hwcg,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 1, 1 },
|
||||
),
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 5, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06050002),
|
||||
.family = ADRENO_6XX_GEN3,
|
||||
.revn = 650,
|
||||
.name = "A650",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a650_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a650_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_1M + SZ_128K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a650_zap.mdt",
|
||||
.hwcg = a650_hwcg,
|
||||
.address_space_size = SZ_16G,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 1, 1 },
|
||||
{ 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
|
||||
{ 3, 2 },
|
||||
),
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 6, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06060001),
|
||||
.family = ADRENO_6XX_GEN4,
|
||||
.revn = 660,
|
||||
.name = "A660",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a660_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a660_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_1M + SZ_512K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a660_zap.mdt",
|
||||
.hwcg = a660_hwcg,
|
||||
.address_space_size = SZ_16G,
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 3, 5, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06030500),
|
||||
.family = ADRENO_6XX_GEN4,
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a660_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a660_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_512K,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV,
|
||||
.init = a6xx_gpu_init,
|
||||
.hwcg = a660_hwcg,
|
||||
.address_space_size = SZ_16G,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 117, 0 },
|
||||
{ 190, 1 },
|
||||
),
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 8, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06080000),
|
||||
.family = ADRENO_6XX_GEN2,
|
||||
.revn = 680,
|
||||
.name = "A680",
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a630_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a640_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_2M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a640_zap.mdt",
|
||||
.hwcg = a640_hwcg,
|
||||
}, {
|
||||
.rev = ADRENO_REV(6, 9, 0, ANY_ID),
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x06090000),
|
||||
.family = ADRENO_6XX_GEN4,
|
||||
.fw = {
|
||||
[ADRENO_FW_SQE] = "a660_sqe.fw",
|
||||
[ADRENO_FW_GMU] = "a690_gmu.bin",
|
||||
[ADRENO_FW_GMU] = "a660_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_4M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV,
|
||||
.init = a6xx_gpu_init,
|
||||
.zapfw = "a690_zap.mdt",
|
||||
.hwcg = a690_hwcg,
|
||||
|
@ -395,34 +506,31 @@ MODULE_FIRMWARE("qcom/a530_zap.mdt");
|
|||
MODULE_FIRMWARE("qcom/a530_zap.b00");
|
||||
MODULE_FIRMWARE("qcom/a530_zap.b01");
|
||||
MODULE_FIRMWARE("qcom/a530_zap.b02");
|
||||
MODULE_FIRMWARE("qcom/a540_gpmu.fw2");
|
||||
MODULE_FIRMWARE("qcom/a619_gmu.bin");
|
||||
MODULE_FIRMWARE("qcom/a630_sqe.fw");
|
||||
MODULE_FIRMWARE("qcom/a630_gmu.bin");
|
||||
MODULE_FIRMWARE("qcom/a630_zap.mbn");
|
||||
MODULE_FIRMWARE("qcom/a640_gmu.bin");
|
||||
MODULE_FIRMWARE("qcom/a650_gmu.bin");
|
||||
MODULE_FIRMWARE("qcom/a650_sqe.fw");
|
||||
MODULE_FIRMWARE("qcom/a660_gmu.bin");
|
||||
MODULE_FIRMWARE("qcom/a660_sqe.fw");
|
||||
MODULE_FIRMWARE("qcom/leia_pfp_470.fw");
|
||||
MODULE_FIRMWARE("qcom/leia_pm4_470.fw");
|
||||
MODULE_FIRMWARE("qcom/yamato_pfp.fw");
|
||||
MODULE_FIRMWARE("qcom/yamato_pm4.fw");
|
||||
|
||||
static inline bool _rev_match(uint8_t entry, uint8_t id)
|
||||
static const struct adreno_info *adreno_info(uint32_t chip_id)
|
||||
{
|
||||
return (entry == ANY_ID) || (entry == id);
|
||||
}
|
||||
|
||||
bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
|
||||
{
|
||||
|
||||
return _rev_match(rev1.core, rev2.core) &&
|
||||
_rev_match(rev1.major, rev2.major) &&
|
||||
_rev_match(rev1.minor, rev2.minor) &&
|
||||
_rev_match(rev1.patchid, rev2.patchid);
|
||||
}
|
||||
|
||||
const struct adreno_info *adreno_info(struct adreno_rev rev)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* identify gpu: */
|
||||
for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
|
||||
for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
|
||||
const struct adreno_info *info = &gpulist[i];
|
||||
if (adreno_cmp_rev(info->rev, rev))
|
||||
return info;
|
||||
if (info->machine && !of_machine_is_compatible(info->machine))
|
||||
continue;
|
||||
for (int j = 0; info->chip_ids[j]; j++)
|
||||
if (info->chip_ids[j] == chip_id)
|
||||
return info;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
|
@ -502,12 +610,11 @@ err_disable_rpm:
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static int find_chipid(struct device *dev, struct adreno_rev *rev)
|
||||
static int find_chipid(struct device *dev, uint32_t *chipid)
|
||||
{
|
||||
struct device_node *node = dev->of_node;
|
||||
const char *compat;
|
||||
int ret;
|
||||
u32 chipid;
|
||||
|
||||
/* first search the compat strings for qcom,adreno-XYZ.W: */
|
||||
ret = of_property_read_string_index(node, "compatible", 0, &compat);
|
||||
|
@ -516,32 +623,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
|
|||
|
||||
if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
|
||||
sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
|
||||
rev->core = r / 100;
|
||||
uint32_t core, major, minor;
|
||||
|
||||
core = r / 100;
|
||||
r %= 100;
|
||||
rev->major = r / 10;
|
||||
major = r / 10;
|
||||
r %= 10;
|
||||
rev->minor = r;
|
||||
rev->patchid = patch;
|
||||
minor = r;
|
||||
|
||||
*chipid = (core << 24) |
|
||||
(major << 16) |
|
||||
(minor << 8) |
|
||||
patch;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* and if that fails, fall back to legacy "qcom,chipid" property: */
|
||||
ret = of_property_read_u32(node, "qcom,chipid", &chipid);
|
||||
ret = of_property_read_u32(node, "qcom,chipid", chipid);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
rev->core = (chipid >> 24) & 0xff;
|
||||
rev->major = (chipid >> 16) & 0xff;
|
||||
rev->minor = (chipid >> 8) & 0xff;
|
||||
rev->patchid = (chipid & 0xff);
|
||||
|
||||
dev_warn(dev, "Using legacy qcom,chipid binding!\n");
|
||||
dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
|
||||
rev->core, rev->major, rev->minor, rev->patchid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -555,26 +664,27 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
|
|||
struct msm_gpu *gpu;
|
||||
int ret;
|
||||
|
||||
ret = find_chipid(dev, &config.rev);
|
||||
ret = find_chipid(dev, &config.chip_id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev->platform_data = &config;
|
||||
priv->gpu_pdev = to_platform_device(dev);
|
||||
|
||||
info = adreno_info(config.rev);
|
||||
|
||||
info = adreno_info(config.chip_id);
|
||||
if (!info) {
|
||||
dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
|
||||
config.rev.core, config.rev.major,
|
||||
config.rev.minor, config.rev.patchid);
|
||||
dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
|
||||
ADRENO_CHIPID_ARGS(config.chip_id));
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
|
||||
config.rev.minor, config.rev.patchid);
|
||||
config.info = info;
|
||||
|
||||
priv->is_a2xx = config.rev.core == 2;
|
||||
DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
|
||||
|
||||
priv->is_a2xx = info->family < ADRENO_3XX;
|
||||
priv->has_cached_coherent =
|
||||
!!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
|
||||
|
||||
gpu = info->init(drm);
|
||||
if (IS_ERR(gpu)) {
|
||||
|
@ -586,10 +696,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (config.rev.core >= 6)
|
||||
if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
|
||||
priv->has_cached_coherent = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -320,16 +320,13 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
|
|||
*value = adreno_gpu->info->revn;
|
||||
return 0;
|
||||
case MSM_PARAM_GMEM_SIZE:
|
||||
*value = adreno_gpu->gmem;
|
||||
*value = adreno_gpu->info->gmem;
|
||||
return 0;
|
||||
case MSM_PARAM_GMEM_BASE:
|
||||
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
|
||||
return 0;
|
||||
case MSM_PARAM_CHIP_ID:
|
||||
*value = (uint64_t)adreno_gpu->rev.patchid |
|
||||
((uint64_t)adreno_gpu->rev.minor << 8) |
|
||||
((uint64_t)adreno_gpu->rev.major << 16) |
|
||||
((uint64_t)adreno_gpu->rev.core << 24);
|
||||
*value = adreno_gpu->chip_id;
|
||||
if (!adreno_gpu->info->revn)
|
||||
*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
|
||||
return 0;
|
||||
|
@ -400,17 +397,9 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
|
|||
case MSM_PARAM_CMDLINE: {
|
||||
char *str, **paramp;
|
||||
|
||||
str = kmalloc(len + 1, GFP_KERNEL);
|
||||
if (!str)
|
||||
return -ENOMEM;
|
||||
|
||||
if (copy_from_user(str, u64_to_user_ptr(value), len)) {
|
||||
kfree(str);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* Ensure string is null terminated: */
|
||||
str[len] = '\0';
|
||||
str = memdup_user_nul(u64_to_user_ptr(value), len);
|
||||
if (IS_ERR(str))
|
||||
return PTR_ERR(str);
|
||||
|
||||
mutex_lock(&gpu->lock);
|
||||
|
||||
|
@ -847,10 +836,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
|
|||
if (IS_ERR_OR_NULL(state))
|
||||
return;
|
||||
|
||||
drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
|
||||
adreno_gpu->info->revn, adreno_gpu->rev.core,
|
||||
adreno_gpu->rev.major, adreno_gpu->rev.minor,
|
||||
adreno_gpu->rev.patchid);
|
||||
drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
|
||||
adreno_gpu->info->revn,
|
||||
ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
|
||||
/*
|
||||
* If this is state collected due to iova fault, so fault related info
|
||||
*
|
||||
|
@ -921,10 +909,9 @@ void adreno_dump_info(struct msm_gpu *gpu)
|
|||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
int i;
|
||||
|
||||
printk("revision: %d (%d.%d.%d.%d)\n",
|
||||
adreno_gpu->info->revn, adreno_gpu->rev.core,
|
||||
adreno_gpu->rev.major, adreno_gpu->rev.minor,
|
||||
adreno_gpu->rev.patchid);
|
||||
printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
|
||||
adreno_gpu->info->revn,
|
||||
ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
|
||||
|
||||
for (i = 0; i < gpu->nr_rings; i++) {
|
||||
struct msm_ringbuffer *ring = gpu->rb[i];
|
||||
|
@ -1041,14 +1028,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
|
|||
return PTR_ERR(ocmem);
|
||||
}
|
||||
|
||||
ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
|
||||
ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem);
|
||||
if (IS_ERR(ocmem_hdl))
|
||||
return PTR_ERR(ocmem_hdl);
|
||||
|
||||
adreno_ocmem->ocmem = ocmem;
|
||||
adreno_ocmem->base = ocmem_hdl->addr;
|
||||
adreno_ocmem->hdl = ocmem_hdl;
|
||||
adreno_gpu->gmem = ocmem_hdl->len;
|
||||
|
||||
if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem))
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1073,13 +1062,19 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
struct adreno_platform_config *config = dev->platform_data;
|
||||
struct msm_gpu_config adreno_gpu_config = { 0 };
|
||||
struct msm_gpu *gpu = &adreno_gpu->base;
|
||||
struct adreno_rev *rev = &config->rev;
|
||||
const char *gpu_name;
|
||||
u32 speedbin;
|
||||
int ret;
|
||||
|
||||
adreno_gpu->funcs = funcs;
|
||||
adreno_gpu->info = config->info;
|
||||
adreno_gpu->chip_id = config->chip_id;
|
||||
|
||||
gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1;
|
||||
|
||||
/* Only handle the core clock when GMU is not in use (or is absent). */
|
||||
if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
|
||||
if (adreno_has_gmu_wrapper(adreno_gpu) ||
|
||||
adreno_gpu->info->family < ADRENO_6XX_GEN1) {
|
||||
/*
|
||||
* This can only be done before devm_pm_opp_of_add_table(), or
|
||||
* dev_pm_opp_set_config() will WARN_ON()
|
||||
|
@ -1095,24 +1090,14 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
devm_pm_opp_set_clkname(dev, "core");
|
||||
}
|
||||
|
||||
adreno_gpu->funcs = funcs;
|
||||
adreno_gpu->info = adreno_info(config->rev);
|
||||
adreno_gpu->gmem = adreno_gpu->info->gmem;
|
||||
adreno_gpu->revn = adreno_gpu->info->revn;
|
||||
adreno_gpu->rev = *rev;
|
||||
|
||||
if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
|
||||
speedbin = 0xffff;
|
||||
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
|
||||
|
||||
gpu_name = adreno_gpu->info->name;
|
||||
if (!gpu_name) {
|
||||
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
|
||||
rev->core, rev->major, rev->minor,
|
||||
rev->patchid);
|
||||
if (!gpu_name)
|
||||
return -ENOMEM;
|
||||
}
|
||||
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
|
||||
ADRENO_CHIPID_ARGS(config->chip_id));
|
||||
if (!gpu_name)
|
||||
return -ENOMEM;
|
||||
|
||||
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
|
||||
|
||||
|
|
|
@ -29,21 +29,40 @@ enum {
|
|||
ADRENO_FW_MAX,
|
||||
};
|
||||
|
||||
/**
|
||||
* @enum adreno_family: identify generation and possibly sub-generation
|
||||
*
|
||||
* In some cases there are distinct sub-generations within a major revision
|
||||
* so it helps to be able to group the GPU devices by generation and if
|
||||
* necessary sub-generation.
|
||||
*/
|
||||
enum adreno_family {
|
||||
ADRENO_2XX_GEN1, /* a20x */
|
||||
ADRENO_2XX_GEN2, /* a22x */
|
||||
ADRENO_3XX,
|
||||
ADRENO_4XX,
|
||||
ADRENO_5XX,
|
||||
ADRENO_6XX_GEN1, /* a630 family */
|
||||
ADRENO_6XX_GEN2, /* a640 family */
|
||||
ADRENO_6XX_GEN3, /* a650 family */
|
||||
ADRENO_6XX_GEN4, /* a660 family */
|
||||
};
|
||||
|
||||
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
|
||||
#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
|
||||
#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
|
||||
#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
|
||||
#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
|
||||
|
||||
struct adreno_rev {
|
||||
uint8_t core;
|
||||
uint8_t major;
|
||||
uint8_t minor;
|
||||
uint8_t patchid;
|
||||
};
|
||||
|
||||
#define ANY_ID 0xff
|
||||
|
||||
#define ADRENO_REV(core, major, minor, patchid) \
|
||||
((struct adreno_rev){ core, major, minor, patchid })
|
||||
/* Helper for formating the chip_id in the way that userspace tools like
|
||||
* crashdec expect.
|
||||
*/
|
||||
#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
|
||||
#define ADRENO_CHIPID_ARGS(_c) \
|
||||
(((_c) >> 24) & 0xff), \
|
||||
(((_c) >> 16) & 0xff), \
|
||||
(((_c) >> 8) & 0xff), \
|
||||
((_c) & 0xff)
|
||||
|
||||
struct adreno_gpu_funcs {
|
||||
struct msm_gpu_funcs base;
|
||||
|
@ -58,10 +77,21 @@ struct adreno_reglist {
|
|||
extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
|
||||
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
|
||||
|
||||
struct adreno_speedbin {
|
||||
uint16_t fuse;
|
||||
uint16_t speedbin;
|
||||
};
|
||||
|
||||
struct adreno_info {
|
||||
struct adreno_rev rev;
|
||||
const char *machine;
|
||||
/**
|
||||
* @chipids: Table of matching chip-ids
|
||||
*
|
||||
* Terminated with 0 sentinal
|
||||
*/
|
||||
uint32_t *chip_ids;
|
||||
enum adreno_family family;
|
||||
uint32_t revn;
|
||||
const char *name;
|
||||
const char *fw[ADRENO_FW_MAX];
|
||||
uint32_t gmem;
|
||||
u64 quirks;
|
||||
|
@ -70,16 +100,39 @@ struct adreno_info {
|
|||
u32 inactive_period;
|
||||
const struct adreno_reglist *hwcg;
|
||||
u64 address_space_size;
|
||||
/**
|
||||
* @speedbins: Optional table of fuse to speedbin mappings
|
||||
*
|
||||
* Consists of pairs of fuse, index mappings, terminated with
|
||||
* {SHRT_MAX, 0} sentinal.
|
||||
*/
|
||||
struct adreno_speedbin *speedbins;
|
||||
};
|
||||
|
||||
const struct adreno_info *adreno_info(struct adreno_rev rev);
|
||||
#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
|
||||
|
||||
/*
|
||||
* Helper to build a speedbin table, ie. the table:
|
||||
* fuse | speedbin
|
||||
* -----+---------
|
||||
* 0 | 0
|
||||
* 169 | 1
|
||||
* 174 | 2
|
||||
*
|
||||
* would be declared as:
|
||||
*
|
||||
* .speedbins = ADRENO_SPEEDBINS(
|
||||
* { 0, 0 },
|
||||
* { 169, 1 },
|
||||
* { 174, 2 },
|
||||
* ),
|
||||
*/
|
||||
#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
|
||||
|
||||
struct adreno_gpu {
|
||||
struct msm_gpu base;
|
||||
struct adreno_rev rev;
|
||||
const struct adreno_info *info;
|
||||
uint32_t gmem; /* actual gmem size */
|
||||
uint32_t revn; /* numeric revision name */
|
||||
uint32_t chip_id;
|
||||
uint16_t speedbin;
|
||||
const struct adreno_gpu_funcs *funcs;
|
||||
|
||||
|
@ -128,7 +181,8 @@ struct adreno_ocmem {
|
|||
|
||||
/* platform config data (ie. from DT, or pdata) */
|
||||
struct adreno_platform_config {
|
||||
struct adreno_rev rev;
|
||||
uint32_t chip_id;
|
||||
const struct adreno_info *info;
|
||||
};
|
||||
|
||||
#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
|
||||
|
@ -145,14 +199,21 @@ struct adreno_platform_config {
|
|||
__ret; \
|
||||
})
|
||||
|
||||
bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
|
||||
static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
|
||||
{
|
||||
/* It is probably ok to assume legacy "adreno_rev" format
|
||||
* for all a6xx devices, but probably best to limit this
|
||||
* to older things.
|
||||
*/
|
||||
WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
|
||||
return gpu->chip_id & 0xff;
|
||||
}
|
||||
|
||||
static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
|
||||
{
|
||||
/* revn can be zero, but if not is set at same time as info */
|
||||
WARN_ON_ONCE(!gpu->info);
|
||||
|
||||
return gpu->revn == revn;
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->revn == revn;
|
||||
}
|
||||
|
||||
static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
|
||||
|
@ -162,18 +223,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
|
|||
|
||||
static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
|
||||
{
|
||||
/* revn can be zero, but if not is set at same time as info */
|
||||
WARN_ON_ONCE(!gpu->info);
|
||||
|
||||
return (gpu->revn < 300);
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->family <= ADRENO_2XX_GEN2;
|
||||
}
|
||||
|
||||
static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
|
||||
{
|
||||
/* revn can be zero, but if not is set at same time as info */
|
||||
WARN_ON_ONCE(!gpu->info);
|
||||
|
||||
return (gpu->revn < 210);
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->family == ADRENO_2XX_GEN1;
|
||||
}
|
||||
|
||||
static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
|
||||
|
@ -204,7 +263,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
|
|||
|
||||
static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
|
||||
{
|
||||
return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
|
||||
return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
|
||||
}
|
||||
|
||||
static inline int adreno_is_a405(const struct adreno_gpu *gpu)
|
||||
|
@ -294,8 +353,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
|
|||
|
||||
static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
|
||||
{
|
||||
/* The order of args is important here to handle ANY_ID correctly */
|
||||
return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
|
||||
return gpu->info->chip_ids[0] == 0x06030500;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a660(const struct adreno_gpu *gpu)
|
||||
|
@ -310,35 +368,37 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
|
|||
|
||||
static inline int adreno_is_a690(const struct adreno_gpu *gpu)
|
||||
{
|
||||
/* The order of args is important here to handle ANY_ID correctly */
|
||||
return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
|
||||
};
|
||||
return gpu->info->chip_ids[0] == 0x06090000;
|
||||
}
|
||||
|
||||
/* check for a615, a616, a618, a619 or any derivatives */
|
||||
static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
|
||||
/* check for a615, a616, a618, a619 or any a630 derivatives */
|
||||
static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
|
||||
{
|
||||
return adreno_is_revn(gpu, 615) ||
|
||||
adreno_is_revn(gpu, 616) ||
|
||||
adreno_is_revn(gpu, 618) ||
|
||||
adreno_is_revn(gpu, 619);
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->family == ADRENO_6XX_GEN1;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
|
||||
{
|
||||
return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->family == ADRENO_6XX_GEN4;
|
||||
}
|
||||
|
||||
/* check for a650, a660, or any derivatives */
|
||||
static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
|
||||
{
|
||||
return adreno_is_revn(gpu, 650) ||
|
||||
adreno_is_revn(gpu, 620) ||
|
||||
adreno_is_a660_family(gpu);
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->family >= ADRENO_6XX_GEN3;
|
||||
}
|
||||
|
||||
static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
|
||||
{
|
||||
return adreno_is_a640(gpu) || adreno_is_a680(gpu);
|
||||
if (WARN_ON_ONCE(!gpu->info))
|
||||
return false;
|
||||
return gpu->info->family == ADRENO_6XX_GEN2;
|
||||
}
|
||||
|
||||
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
|
||||
|
|
|
@ -21,136 +21,257 @@ static const struct dpu_caps msm8998_dpu_caps = {
|
|||
.max_vdeci_exp = MAX_VERT_DECIMATION,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_10,
|
||||
.highest_bank_bit = 0x2,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg msm8998_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg msm8998_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x458,
|
||||
.features = BIT(DPU_MDP_VSYNC_SEL),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
|
||||
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
|
||||
[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg msm8998_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x94,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x94,
|
||||
.features = 0,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x94,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x94,
|
||||
.features = 0,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x94,
|
||||
.features = 0,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x94,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x94,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x94,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x94,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x94,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg msm8998_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
|
||||
msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
|
||||
msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
|
||||
msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
|
||||
msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1ac,
|
||||
.features = VIG_MSM8998_MASK,
|
||||
.sblk = &msm8998_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x1ac,
|
||||
.features = VIG_MSM8998_MASK,
|
||||
.sblk = &msm8998_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x1ac,
|
||||
.features = VIG_MSM8998_MASK,
|
||||
.sblk = &msm8998_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x1ac,
|
||||
.features = VIG_MSM8998_MASK,
|
||||
.sblk = &msm8998_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1ac,
|
||||
.features = DMA_MSM8998_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1ac,
|
||||
.features = DMA_MSM8998_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1ac,
|
||||
.features = DMA_CURSOR_MSM8998_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x1ac,
|
||||
.features = DMA_CURSOR_MSM8998_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg msm8998_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
|
||||
&msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
|
||||
&msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
|
||||
&msm8998_lm_sblk, PINGPONG_2, LM_5, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
|
||||
&msm8998_lm_sblk, PINGPONG_NONE, 0, 0),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
|
||||
&msm8998_lm_sblk, PINGPONG_NONE, 0, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
|
||||
&msm8998_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &msm8998_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &msm8998_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &msm8998_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &msm8998_lm_sblk,
|
||||
.pingpong = PINGPONG_NONE,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &msm8998_lm_sblk,
|
||||
.pingpong = PINGPONG_NONE,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &msm8998_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg msm8998_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_TE2_MASK,
|
||||
.sblk = &sdm845_pp_sblk_te,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_TE2_MASK,
|
||||
.sblk = &sdm845_pp_sblk_te,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x71000, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x71800, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg msm8998_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
|
||||
DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
}, {
|
||||
.name = "dsc_1", .id = DSC_1,
|
||||
.base = 0x80400, .len = 0x140,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg msm8998_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&msm8998_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&msm8998_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &msm8998_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &msm8998_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg msm8998_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
|
||||
INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 21,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x280,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 21,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x6b000, .len = 0x280,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 21,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_HDMI,
|
||||
.prog_fetch_lines_worst_case = 21,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg msm8998_perf_data = {
|
||||
|
@ -189,11 +310,15 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version msm8998_mdss_ver = {
|
||||
.core_major_ver = 3,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_msm8998_cfg = {
|
||||
.mdss_ver = &msm8998_mdss_ver,
|
||||
.caps = &msm8998_dpu_caps,
|
||||
.ubwc = &msm8998_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(msm8998_mdp),
|
||||
.mdp = msm8998_mdp,
|
||||
.mdp = &msm8998_mdp,
|
||||
.ctl_count = ARRAY_SIZE(msm8998_ctl),
|
||||
.ctl = msm8998_ctl,
|
||||
.sspp_count = ARRAY_SIZE(msm8998_sspp),
|
||||
|
@ -211,14 +336,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(msm8998_vbif),
|
||||
.vbif = msm8998_vbif,
|
||||
.perf = &msm8998_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF2_INTR) | \
|
||||
BIT(MDP_INTF3_INTR) | \
|
||||
BIT(MDP_INTF4_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,140 +21,274 @@ static const struct dpu_caps sdm845_dpu_caps = {
|
|||
.max_vdeci_exp = MAX_VERT_DECIMATION,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_20,
|
||||
.highest_bank_bit = 0x2,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sdm845_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sdm845_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x45c,
|
||||
.features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sdm845_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0xe4,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0xe4,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0xe4,
|
||||
.features = 0,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0xe4,
|
||||
.features = 0,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0xe4,
|
||||
.features = 0,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0xe4,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0xe4,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0xe4,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0xe4,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0xe4,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sdm845_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
|
||||
sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
|
||||
sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
|
||||
sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
|
||||
sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1c8,
|
||||
.features = VIG_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x1c8,
|
||||
.features = VIG_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x1c8,
|
||||
.features = VIG_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x1c8,
|
||||
.features = VIG_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1c8,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1c8,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1c8,
|
||||
.features = DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x1c8,
|
||||
.features = DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sdm845_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_5, DSPP_2),
|
||||
LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_NONE, 0, DSPP_3),
|
||||
LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_NONE, 0, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_2,
|
||||
.dspp = DSPP_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x0, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.pingpong = PINGPONG_NONE,
|
||||
.dspp = DSPP_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x0, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.pingpong = PINGPONG_NONE,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sdm845_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sdm845_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_TE2_MASK,
|
||||
.sblk = &sdm845_pp_sblk_te,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_TE2_MASK,
|
||||
.sblk = &sdm845_pp_sblk_te,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x71000, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x71800, .len = 0xd4,
|
||||
.features = PINGPONG_SDM845_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg sdm845_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
|
||||
DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
|
||||
DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
|
||||
DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
}, {
|
||||
.name = "dsc_1", .id = DSC_1,
|
||||
.base = 0x80400, .len = 0x140,
|
||||
}, {
|
||||
.name = "dsc_2", .id = DSC_2,
|
||||
.base = 0x80800, .len = 0x140,
|
||||
}, {
|
||||
.name = "dsc_3", .id = DSC_3,
|
||||
.base = 0x80c00, .len = 0x140,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sdm845_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
|
||||
INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x280,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x6b000, .len = 0x280,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sdm845_perf_data = {
|
||||
|
@ -193,11 +327,15 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sdm845_mdss_ver = {
|
||||
.core_major_ver = 4,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sdm845_cfg = {
|
||||
.mdss_ver = &sdm845_mdss_ver,
|
||||
.caps = &sdm845_dpu_caps,
|
||||
.ubwc = &sdm845_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sdm845_mdp),
|
||||
.mdp = sdm845_mdp,
|
||||
.mdp = &sdm845_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sdm845_ctl),
|
||||
.ctl = sdm845_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sdm845_sspp),
|
||||
|
@ -215,15 +353,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sdm845_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF2_INTR) | \
|
||||
BIT(MDP_INTF3_INTR) | \
|
||||
BIT(MDP_AD4_0_INTR) | \
|
||||
BIT(MDP_AD4_1_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,161 +21,324 @@ static const struct dpu_caps sm8150_dpu_caps = {
|
|||
.max_vdeci_exp = MAX_VERT_DECIMATION,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_30,
|
||||
.highest_bank_bit = 0x2,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm8150_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm8150_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x45c,
|
||||
.features = BIT(DPU_MDP_AUDIO_SELECT),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
|
||||
static const struct dpu_ctl_cfg sm8150_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm8150_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f0,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f0,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f0,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x1f0,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm8150_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm8150_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm8150_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
-1),
|
||||
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x71000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x71800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x72000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x72800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x83000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x83100, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x83200, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg sm8150_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_1", .id = DSC_1,
|
||||
.base = 0x80400, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_2", .id = DSC_2,
|
||||
.base = 0x80800, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_3", .id = DSC_3,
|
||||
.base = 0x80c00, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm8150_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2bc,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x6b000, .len = 0x2bc,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8150_perf_data = {
|
||||
|
@ -207,11 +370,15 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm8150_mdss_ver = {
|
||||
.core_major_ver = 5,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm8150_cfg = {
|
||||
.mdss_ver = &sm8150_mdss_ver,
|
||||
.caps = &sm8150_dpu_caps,
|
||||
.ubwc = &sm8150_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm8150_mdp),
|
||||
.mdp = sm8150_mdp,
|
||||
.mdp = &sm8150_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm8150_ctl),
|
||||
.ctl = sm8150_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm8150_sspp),
|
||||
|
@ -231,17 +398,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm8150_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_INTR) | \
|
||||
BIT(MDP_INTF2_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_INTR) | \
|
||||
BIT(MDP_AD4_0_INTR) | \
|
||||
BIT(MDP_AD4_1_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,169 +21,353 @@ static const struct dpu_caps sc8180x_dpu_caps = {
|
|||
.max_vdeci_exp = MAX_VERT_DECIMATION,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_30,
|
||||
.highest_bank_bit = 0x3,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sc8180x_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sc8180x_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x45c,
|
||||
.features = BIT(DPU_MDP_AUDIO_SELECT),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sc8180x_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sc8180x_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
|
||||
sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x1f0,
|
||||
.features = VIG_SDM845_MASK,
|
||||
.sblk = &sdm845_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f0,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f0,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f0,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x1f0,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sc8180x_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sc8180x_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sc8180x_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
-1),
|
||||
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x71000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x71800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x72000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x72800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x83000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x83100, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x83200, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg sc8180x_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_1", .id = DSC_1,
|
||||
.base = 0x80400, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_2", .id = DSC_2,
|
||||
.base = 0x80800, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_3", .id = DSC_3,
|
||||
.base = 0x80c00, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_4", .id = DSC_4,
|
||||
.base = 0x81000, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_5", .id = DSC_5,
|
||||
.base = 0x81400, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sc8180x_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2bc,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x6b000, .len = 0x2bc,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
},
|
||||
/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
|
||||
INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
|
||||
INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
|
||||
{
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = 999,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_4", .id = INTF_4,
|
||||
.base = 0x6c000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_5", .id = INTF_5,
|
||||
.base = 0x6c800, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_2,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sc8180x_perf_data = {
|
||||
|
@ -213,11 +397,15 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sc8180x_mdss_ver = {
|
||||
.core_major_ver = 5,
|
||||
.core_minor_ver = 1,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
|
||||
.mdss_ver = &sc8180x_mdss_ver,
|
||||
.caps = &sc8180x_dpu_caps,
|
||||
.ubwc = &sc8180x_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sc8180x_mdp),
|
||||
.mdp = sc8180x_mdp,
|
||||
.mdp = &sc8180x_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sc8180x_ctl),
|
||||
.ctl = sc8180x_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sc8180x_sspp),
|
||||
|
@ -237,19 +425,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sc8180x_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_INTR) | \
|
||||
BIT(MDP_INTF2_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_INTR) | \
|
||||
BIT(MDP_INTF4_INTR) | \
|
||||
BIT(MDP_INTF5_INTR) | \
|
||||
BIT(MDP_AD4_0_INTR) | \
|
||||
BIT(MDP_AD4_1_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -0,0 +1,223 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved.
|
||||
* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DPU_5_4_SM6125_H
|
||||
#define _DPU_5_4_SM6125_H
|
||||
|
||||
static const struct dpu_caps sm6125_dpu_caps = {
|
||||
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
|
||||
.max_mixer_blendstages = 0x6,
|
||||
.has_dim_layer = true,
|
||||
.has_idle_pc = true,
|
||||
.max_linewidth = 2160,
|
||||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
.max_hdeci_exp = MAX_HORZ_DECIMATION,
|
||||
.max_vdeci_exp = MAX_VERT_DECIMATION,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm6125_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x45c,
|
||||
.features = 0,
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sm6125_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm6125_sspp[] = {
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f0,
|
||||
.features = VIG_SM6125_MASK,
|
||||
.sblk = &sm6125_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f0,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f0,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm6125_lm[] = {
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_QCM2290_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
.lm_pair = LM_1,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_QCM2290_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = 0,
|
||||
.lm_pair = LM_0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm6125_dspp[] = {
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm6125_pp[] = {
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.merge_3d = 0,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.merge_3d = 0,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm6125_intf[] = {
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = 0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm6125_perf_data = {
|
||||
.max_bw_low = 4100000,
|
||||
.max_bw_high = 4100000,
|
||||
.min_core_ib = 2400000,
|
||||
.min_llcc_ib = 0, /* No LLCC on this SoC */
|
||||
.min_dram_ib = 800000,
|
||||
.min_prefill_lines = 24,
|
||||
.danger_lut_tbl = {0xf, 0xffff, 0x0},
|
||||
.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
|
||||
.qos_lut_tbl = {
|
||||
{.nentry = ARRAY_SIZE(sm8150_qos_linear),
|
||||
.entries = sm8150_qos_linear
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
|
||||
.entries = sc7180_qos_macrotile
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
|
||||
.entries = sc7180_qos_nrt
|
||||
},
|
||||
/* TODO: macrotile-qseed is different from macrotile */
|
||||
},
|
||||
.cdp_cfg = {
|
||||
{.rd_enable = 1, .wr_enable = 1},
|
||||
{.rd_enable = 1, .wr_enable = 0}
|
||||
},
|
||||
.clk_inefficiency_factor = 105,
|
||||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm6125_mdss_ver = {
|
||||
.core_major_ver = 5,
|
||||
.core_minor_ver = 4,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm6125_cfg = {
|
||||
.mdss_ver = &sm6125_mdss_ver,
|
||||
.caps = &sm6125_dpu_caps,
|
||||
.mdp = &sm6125_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm6125_ctl),
|
||||
.ctl = sm6125_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm6125_sspp),
|
||||
.sspp = sm6125_sspp,
|
||||
.mixer_count = ARRAY_SIZE(sm6125_lm),
|
||||
.mixer = sm6125_lm,
|
||||
.dspp_count = ARRAY_SIZE(sm6125_dspp),
|
||||
.dspp = sm6125_dspp,
|
||||
.pingpong_count = ARRAY_SIZE(sm6125_pp),
|
||||
.pingpong = sm6125_pp,
|
||||
.intf_count = ARRAY_SIZE(sm6125_intf),
|
||||
.intf = sm6125_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm6125_perf_data,
|
||||
};
|
||||
|
||||
#endif
|
|
@ -19,169 +19,340 @@ static const struct dpu_caps sm8250_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_40,
|
||||
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
|
||||
.ubwc_swizzle = 0x6,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm8250_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm8250_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
|
||||
static const struct dpu_ctl_cfg sm8250_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x1800, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a00, .len = 0x1e0,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm8250_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
|
||||
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
|
||||
sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
|
||||
sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
|
||||
sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK_SDMA,
|
||||
.sblk = &sm8250_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK_SDMA,
|
||||
.sblk = &sm8250_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK_SDMA,
|
||||
.sblk = &sm8250_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK_SDMA,
|
||||
.sblk = &sm8250_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm8250_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm8250_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm8250_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
-1),
|
||||
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x71000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x71800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x72000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x72800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x83000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x83100, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x83200, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg sm8250_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_1", .id = DSC_1,
|
||||
.base = 0x80400, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_2", .id = DSC_2,
|
||||
.base = 0x80800, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
}, {
|
||||
.name = "dsc_3", .id = DSC_3,
|
||||
.base = 0x80c00, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm8250_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x6b000, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_wb_cfg sm8250_wb[] = {
|
||||
WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
|
||||
VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
|
||||
{
|
||||
.name = "wb_2", .id = WB_2,
|
||||
.base = 0x65000, .len = 0x2c8,
|
||||
.features = WB_SM8250_MASK,
|
||||
.format_list = wb2_formats,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8250_perf_data = {
|
||||
|
@ -213,11 +384,15 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm8250_mdss_ver = {
|
||||
.core_major_ver = 6,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm8250_cfg = {
|
||||
.mdss_ver = &sm8250_mdss_ver,
|
||||
.caps = &sm8250_dpu_caps,
|
||||
.ubwc = &sm8250_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm8250_mdp),
|
||||
.mdp = sm8250_mdp,
|
||||
.mdp = &sm8250_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm8250_ctl),
|
||||
.ctl = sm8250_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm8250_sspp),
|
||||
|
@ -239,16 +414,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
|
|||
.wb_count = ARRAY_SIZE(sm8250_wb),
|
||||
.wb = sm8250_wb,
|
||||
.perf = &sm8250_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_INTR) | \
|
||||
BIT(MDP_INTF2_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_INTR) | \
|
||||
BIT(MDP_INTF4_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -17,90 +17,158 @@ static const struct dpu_caps sc7180_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_20,
|
||||
.highest_bank_bit = 0x3,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sc7180_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sc7180_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sc7180_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sc7180_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
|
||||
sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sc7180_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sc7180_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sc7180_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sc7180_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sc7180_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_wb_cfg sc7180_wb[] = {
|
||||
WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
|
||||
VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
|
||||
{
|
||||
.name = "wb_2", .id = WB_2,
|
||||
.base = 0x65000, .len = 0x2c8,
|
||||
.features = WB_SM8250_MASK,
|
||||
.format_list = wb2_formats,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sc7180_perf_data = {
|
||||
|
@ -131,11 +199,15 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sc7180_mdss_ver = {
|
||||
.core_major_ver = 6,
|
||||
.core_minor_ver = 2,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sc7180_cfg = {
|
||||
.mdss_ver = &sc7180_mdss_ver,
|
||||
.caps = &sc7180_dpu_caps,
|
||||
.ubwc = &sc7180_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sc7180_mdp),
|
||||
.mdp = sc7180_mdp,
|
||||
.mdp = &sc7180_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sc7180_ctl),
|
||||
.ctl = sc7180_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sc7180_sspp),
|
||||
|
@ -153,12 +225,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sc7180_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -17,59 +17,88 @@ static const struct dpu_caps sm6115_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_10,
|
||||
.highest_bank_bit = 0x1,
|
||||
.ubwc_swizzle = 0x7,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm6115_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm6115_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sm6115_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm6115_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
|
||||
sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm6115_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm6115_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
|
||||
&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_QCM2290_MASK,
|
||||
.sblk = &qcm2290_lm_sblk,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm6115_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm6115_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm6115_intf[] = {
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
{
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm6115_perf_data = {
|
||||
|
@ -101,11 +130,15 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm6115_mdss_ver = {
|
||||
.core_major_ver = 6,
|
||||
.core_minor_ver = 3,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm6115_cfg = {
|
||||
.mdss_ver = &sm6115_mdss_ver,
|
||||
.caps = &sm6115_dpu_caps,
|
||||
.ubwc = &sm6115_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm6115_mdp),
|
||||
.mdp = sm6115_mdp,
|
||||
.mdp = &sm6115_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm6115_ctl),
|
||||
.ctl = sm6115_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm6115_sspp),
|
||||
|
@ -121,11 +154,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm6115_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -19,96 +19,157 @@ static const struct dpu_caps sm6350_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_20,
|
||||
.ubwc_swizzle = 6,
|
||||
.highest_bank_bit = 1,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm6350_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm6350_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sm6350_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x1200, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x1400, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x1600, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm6350_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
|
||||
sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sc7180_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm6350_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm6350_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static struct dpu_pingpong_cfg sm6350_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x70800, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg sm6350_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm6350_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x280,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 35,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 35,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm6350_perf_data = {
|
||||
|
@ -140,11 +201,15 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm6350_mdss_ver = {
|
||||
.core_major_ver = 6,
|
||||
.core_minor_ver = 4,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm6350_cfg = {
|
||||
.mdss_ver = &sm6350_mdss_ver,
|
||||
.caps = &sm6350_dpu_caps,
|
||||
.ubwc = &sm6350_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm6350_mdp),
|
||||
.mdp = sm6350_mdp,
|
||||
.mdp = &sm6350_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm6350_ctl),
|
||||
.ctl = sm6350_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm6350_sspp),
|
||||
|
@ -162,12 +227,6 @@ const struct dpu_mdss_cfg dpu_sm6350_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm6350_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -16,57 +16,88 @@ static const struct dpu_caps qcm2290_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
|
||||
.highest_bank_bit = 0x2,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg qcm2290_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg qcm2290_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg qcm2290_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg qcm2290_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
|
||||
qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
|
||||
qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_QCM2290_MASK,
|
||||
.sblk = &qcm2290_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &qcm2290_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg qcm2290_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
|
||||
&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_QCM2290_MASK,
|
||||
.sblk = &qcm2290_lm_sblk,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg qcm2290_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg qcm2290_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg qcm2290_intf[] = {
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
{
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg qcm2290_perf_data = {
|
||||
|
@ -91,11 +122,15 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version qcm2290_mdss_ver = {
|
||||
.core_major_ver = 6,
|
||||
.core_minor_ver = 5,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
|
||||
.mdss_ver = &qcm2290_mdss_ver,
|
||||
.caps = &qcm2290_dpu_caps,
|
||||
.ubwc = &qcm2290_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(qcm2290_mdp),
|
||||
.mdp = qcm2290_mdp,
|
||||
.mdp = &qcm2290_mdp,
|
||||
.ctl_count = ARRAY_SIZE(qcm2290_ctl),
|
||||
.ctl = qcm2290_ctl,
|
||||
.sspp_count = ARRAY_SIZE(qcm2290_sspp),
|
||||
|
@ -111,11 +146,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &qcm2290_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -18,63 +18,97 @@ static const struct dpu_caps sm6375_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_20,
|
||||
.ubwc_swizzle = 6,
|
||||
.highest_bank_bit = 1,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm6375_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm6375_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sm6375_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x1000, .len = 0x1dc,
|
||||
.features = BIT(DPU_CTL_ACTIVE_CFG),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm6375_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
|
||||
sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm6115_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm6375_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
|
||||
&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_QCM2290_MASK,
|
||||
.sblk = &qcm2290_lm_sblk,
|
||||
.lm_pair = 0,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm6375_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm6375_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x70000, .len = 0xd4,
|
||||
.features = PINGPONG_SM8150_MASK,
|
||||
.sblk = &sdm845_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_cfg sm6375_dsc[] = {
|
||||
DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
|
||||
{
|
||||
.name = "dsc_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x140,
|
||||
.features = BIT(DPU_DSC_OUTPUT_CTRL),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm6375_intf[] = {
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
|
||||
{
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x2c0,
|
||||
.features = INTF_SC7180_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm6375_perf_data = {
|
||||
|
@ -106,11 +140,15 @@ static const struct dpu_perf_cfg sm6375_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm6375_mdss_ver = {
|
||||
.core_major_ver = 6,
|
||||
.core_minor_ver = 9,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm6375_cfg = {
|
||||
.mdss_ver = &sm6375_mdss_ver,
|
||||
.caps = &sm6375_dpu_caps,
|
||||
.ubwc = &sm6375_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm6375_mdp),
|
||||
.mdp = sm6375_mdp,
|
||||
.mdp = &sm6375_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm6375_ctl),
|
||||
.ctl = sm6375_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm6375_sspp),
|
||||
|
@ -128,11 +166,6 @@ const struct dpu_mdss_cfg dpu_sm6375_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm6375_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF1_INTR) | \
|
||||
BIT(MDP_INTF1_TEAR_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -19,138 +19,260 @@ static const struct dpu_caps sm8350_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_40,
|
||||
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm8350_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm8350_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
|
||||
static const struct dpu_ctl_cfg sm8350_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x1e8,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x1e8,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x1e8,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x1e8,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm8350_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x1f8,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm8350_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm8350_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm8350_pp[] = {
|
||||
PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x69000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x6a000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x6b000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x6c000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x6d000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x6e000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x4e000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x4f000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x50000, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -159,27 +281,71 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
|
|||
* its own different sub block address.
|
||||
*/
|
||||
static const struct dpu_dsc_cfg sm8350_dsc[] = {
|
||||
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
|
||||
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
|
||||
{
|
||||
.name = "dce_0_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_0_1", .id = DSC_1,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_1,
|
||||
}, {
|
||||
.name = "dce_1_0", .id = DSC_2,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_1_1", .id = DSC_3,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm8350_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x2c4,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x36000, .len = 0x2c4,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8350_perf_data = {
|
||||
|
@ -212,11 +378,15 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm8350_mdss_ver = {
|
||||
.core_major_ver = 7,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm8350_cfg = {
|
||||
.mdss_ver = &sm8350_mdss_ver,
|
||||
.caps = &sm8350_dpu_caps,
|
||||
.ubwc = &sm8350_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm8350_mdp),
|
||||
.mdp = sm8350_mdp,
|
||||
.mdp = &sm8350_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm8350_ctl),
|
||||
.ctl = sm8350_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm8350_sspp),
|
||||
|
@ -236,15 +406,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm8350_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_7xxx_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -17,112 +17,205 @@ static const struct dpu_caps sc7280_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_30,
|
||||
.highest_bank_bit = 0x1,
|
||||
.ubwc_swizzle = 0x6,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sc7280_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sc7280_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x2014,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg sc7280_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x1e8,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sc7280_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA,
|
||||
sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x1f8,
|
||||
.features = VIG_SC7280_MASK_SDMA,
|
||||
.sblk = &sc7280_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x1f8,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x1f8,
|
||||
.features = DMA_CURSOR_SDM845_MASK_SDMA,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sc7280_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sc7180_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sc7280_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sc7280_pp[] = {
|
||||
PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x69000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x6a000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x6b000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x6c000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = 0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
/* NOTE: sc7280 only has one DSC hard slice encoder */
|
||||
static const struct dpu_dsc_cfg sc7280_dsc[] = {
|
||||
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
|
||||
{
|
||||
.name = "dce_0_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_wb_cfg sc7280_wb[] = {
|
||||
WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
|
||||
VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
|
||||
{
|
||||
.name = "wb_2", .id = WB_2,
|
||||
.base = 0x65000, .len = 0x2c8,
|
||||
.features = WB_SM8250_MASK,
|
||||
.format_list = wb2_formats,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sc7280_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x2c4,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_5", .id = INTF_5,
|
||||
.base = 0x39000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sc7280_perf_data = {
|
||||
|
@ -153,11 +246,15 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sc7280_mdss_ver = {
|
||||
.core_major_ver = 7,
|
||||
.core_minor_ver = 2,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sc7280_cfg = {
|
||||
.mdss_ver = &sc7280_mdss_ver,
|
||||
.caps = &sc7280_dpu_caps,
|
||||
.ubwc = &sc7280_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sc7280_mdp),
|
||||
.mdp = sc7280_mdp,
|
||||
.mdp = &sc7280_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sc7280_ctl),
|
||||
.ctl = sc7280_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sc7280_sspp),
|
||||
|
@ -177,13 +274,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sc7280_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF5_7xxx_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -19,127 +19,263 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_40,
|
||||
.highest_bank_bit = 2,
|
||||
.ubwc_swizzle = 6,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sc8280xp_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
|
||||
static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x2ac,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x2ac,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x2ac,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x2ac,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x2ac,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x2ac,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x2ac,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x2ac,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sc8280xp_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
.dspp = DSPP_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
.dspp = DSPP_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
|
||||
PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
|
||||
PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
|
||||
PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
|
||||
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
|
||||
PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
|
||||
PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x69000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x6a000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x6b000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x6c000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x6d000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x6e000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x4e000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x4f000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x50000, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -148,45 +284,132 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
|
|||
* its own different sub block address.
|
||||
*/
|
||||
static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
|
||||
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
|
||||
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
|
||||
DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1),
|
||||
{
|
||||
.name = "dce_0_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_0_1", .id = DSC_1,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_1,
|
||||
}, {
|
||||
.name = "dce_1_0", .id = DSC_2,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_1_1", .id = DSC_3,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_1,
|
||||
}, {
|
||||
.name = "dce_2_0", .id = DSC_4,
|
||||
.base = 0x82000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_2_1", .id = DSC_5,
|
||||
.base = 0x82000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_1,
|
||||
},
|
||||
};
|
||||
|
||||
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
|
||||
static const struct dpu_intf_cfg sc8280xp_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
|
||||
INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
|
||||
INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17)),
|
||||
INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19)),
|
||||
INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x300,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x36000, .len = 0x300,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_NONE,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_4", .id = INTF_4,
|
||||
.base = 0x38000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_5", .id = INTF_5,
|
||||
.base = 0x39000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_3,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_6", .id = INTF_6,
|
||||
.base = 0x3a000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_2,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_7", .id = INTF_7,
|
||||
.base = 0x3b000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_NONE,
|
||||
.controller_id = MSM_DP_CONTROLLER_2,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_8", .id = INTF_8,
|
||||
.base = 0x3c000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_NONE,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sc8280xp_perf_data = {
|
||||
|
@ -216,11 +439,15 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sc8280xp_mdss_ver = {
|
||||
.core_major_ver = 8,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
|
||||
.mdss_ver = &sc8280xp_mdss_ver,
|
||||
.caps = &sc8280xp_dpu_caps,
|
||||
.ubwc = &sc8280xp_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sc8280xp_mdp),
|
||||
.mdp = sc8280xp_mdp,
|
||||
.mdp = &sc8280xp_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sc8280xp_ctl),
|
||||
.ctl = sc8280xp_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sc8280xp_sspp),
|
||||
|
@ -240,20 +467,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sc8280xp_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_7xxx_INTR) | \
|
||||
BIT(MDP_INTF4_7xxx_INTR) | \
|
||||
BIT(MDP_INTF5_7xxx_INTR) | \
|
||||
BIT(MDP_INTF6_7xxx_INTR) | \
|
||||
BIT(MDP_INTF7_7xxx_INTR) | \
|
||||
BIT(MDP_INTF8_7xxx_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -19,146 +19,282 @@ static const struct dpu_caps sm8450_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_40,
|
||||
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
|
||||
.ubwc_swizzle = 0x6,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm8450_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm8450_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
|
||||
static const struct dpu_ctl_cfg sm8450_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x204,
|
||||
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x204,
|
||||
.features = CTL_SC7280_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm8450_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK,
|
||||
sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x32c,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x32c,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x32c,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x32c,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8250_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x32c,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x32c,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x32c,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x32c,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm8450_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
.dspp = DSPP_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
.dspp = DSPP_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm8450_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sm8450_pp[] = {
|
||||
PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk,
|
||||
-1,
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk,
|
||||
-1,
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x69000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x6a000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x6b000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x6c000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x6d000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x6e000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_6", .id = PINGPONG_6,
|
||||
.base = 0x65800, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_3,
|
||||
.intr_done = -1,
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_7", .id = PINGPONG_7,
|
||||
.base = 0x65c00, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_3,
|
||||
.intr_done = -1,
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
|
||||
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x4e000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x4f000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x50000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_3", .id = MERGE_3D_3,
|
||||
.base = 0x65f00, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -167,27 +303,71 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
|
|||
* its own different sub block address.
|
||||
*/
|
||||
static const struct dpu_dsc_cfg sm8450_dsc[] = {
|
||||
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
|
||||
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
|
||||
{
|
||||
.name = "dce_0_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_0_1", .id = DSC_1,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_1,
|
||||
}, {
|
||||
.name = "dce_1_0", .id = DSC_2,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_1_1", .id = DSC_3,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm8450_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x300,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x36000, .len = 0x300,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8450_perf_data = {
|
||||
|
@ -220,11 +400,15 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm8450_mdss_ver = {
|
||||
.core_major_ver = 8,
|
||||
.core_minor_ver = 1,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm8450_cfg = {
|
||||
.mdss_ver = &sm8450_mdss_ver,
|
||||
.caps = &sm8450_dpu_caps,
|
||||
.ubwc = &sm8450_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm8450_mdp),
|
||||
.mdp = sm8450_mdp,
|
||||
.mdp = &sm8450_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm8450_ctl),
|
||||
.ctl = sm8450_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm8450_sspp),
|
||||
|
@ -244,15 +428,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
|
|||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm8450_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_7xxx_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -19,150 +19,297 @@ static const struct dpu_caps sm8550_dpu_caps = {
|
|||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = {
|
||||
.ubwc_version = DPU_HW_UBWC_VER_40,
|
||||
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm8550_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
static const struct dpu_mdp_cfg sm8550_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0, .len = 0x494,
|
||||
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
|
||||
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
},
|
||||
};
|
||||
|
||||
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
|
||||
static const struct dpu_ctl_cfg sm8550_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
},
|
||||
{
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
},
|
||||
{
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
},
|
||||
{
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
{
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
},
|
||||
{
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
}, {
|
||||
.name = "ctl_4", .id = CTL_4,
|
||||
.base = 0x19000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
|
||||
}, {
|
||||
.name = "ctl_5", .id = CTL_5,
|
||||
.base = 0x1a000, .len = 0x290,
|
||||
.features = CTL_SM8550_MASK,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg sm8550_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
|
||||
sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
|
||||
sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
|
||||
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
|
||||
sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
|
||||
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
|
||||
sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
|
||||
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
|
||||
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
|
||||
SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
|
||||
sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
|
||||
SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
|
||||
sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x344,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8550_vig_sblk_0,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG0,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x344,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8550_vig_sblk_1,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG1,
|
||||
}, {
|
||||
.name = "sspp_2", .id = SSPP_VIG2,
|
||||
.base = 0x8000, .len = 0x344,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8550_vig_sblk_2,
|
||||
.xin_id = 8,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG2,
|
||||
}, {
|
||||
.name = "sspp_3", .id = SSPP_VIG3,
|
||||
.base = 0xa000, .len = 0x344,
|
||||
.features = VIG_SC7180_MASK,
|
||||
.sblk = &sm8550_vig_sblk_3,
|
||||
.xin_id = 12,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
.clk_ctrl = DPU_CLK_CTRL_VIG3,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_0,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA0,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_1,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA1,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_2,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA2,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK,
|
||||
.sblk = &sdm845_dma_sblk_3,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA3,
|
||||
}, {
|
||||
.name = "sspp_12", .id = SSPP_DMA4,
|
||||
.base = 0x2c000, .len = 0x344,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sm8550_dma_sblk_4,
|
||||
.xin_id = 14,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA4,
|
||||
}, {
|
||||
.name = "sspp_13", .id = SSPP_DMA5,
|
||||
.base = 0x2e000, .len = 0x344,
|
||||
.features = DMA_CURSOR_SDM845_MASK,
|
||||
.sblk = &sm8550_dma_sblk_5,
|
||||
.xin_id = 15,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
.clk_ctrl = DPU_CLK_CTRL_DMA5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg sm8550_lm[] = {
|
||||
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
|
||||
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
|
||||
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
|
||||
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
|
||||
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
|
||||
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
|
||||
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
}, {
|
||||
.name = "lm_4", .id = LM_4,
|
||||
.base = 0x48000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_5,
|
||||
.pingpong = PINGPONG_4,
|
||||
}, {
|
||||
.name = "lm_5", .id = LM_5,
|
||||
.base = 0x49000, .len = 0x320,
|
||||
.features = MIXER_SDM845_MASK,
|
||||
.sblk = &sdm845_lm_sblk,
|
||||
.lm_pair = LM_4,
|
||||
.pingpong = PINGPONG_5,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg sm8550_dspp[] = {
|
||||
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
|
||||
&sm8150_dspp_sblk),
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_3", .id = DSPP_3,
|
||||
.base = 0x5a000, .len = 0x1800,
|
||||
.features = DSPP_SC7180_MASK,
|
||||
.sblk = &sdm845_dspp_sblk,
|
||||
},
|
||||
};
|
||||
static const struct dpu_pingpong_cfg sm8550_pp[] = {
|
||||
PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk,
|
||||
-1,
|
||||
-1),
|
||||
PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk,
|
||||
-1,
|
||||
-1),
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x69000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x6a000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x6b000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x6c000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_4", .id = PINGPONG_4,
|
||||
.base = 0x6d000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_5", .id = PINGPONG_5,
|
||||
.base = 0x6e000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_6", .id = PINGPONG_6,
|
||||
.base = 0x66000, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_3,
|
||||
.intr_done = -1,
|
||||
.intr_rdptr = -1,
|
||||
}, {
|
||||
.name = "pingpong_7", .id = PINGPONG_7,
|
||||
.base = 0x66400, .len = 0,
|
||||
.features = BIT(DPU_PINGPONG_DITHER),
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_3,
|
||||
.intr_done = -1,
|
||||
.intr_rdptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
|
||||
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
|
||||
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x4e000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x4f000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x50000, .len = 0x8,
|
||||
}, {
|
||||
.name = "merge_3d_3", .id = MERGE_3D_3,
|
||||
.base = 0x66700, .len = 0x8,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -171,27 +318,71 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
|
|||
* its own different sub block address.
|
||||
*/
|
||||
static const struct dpu_dsc_cfg sm8550_dsc[] = {
|
||||
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
|
||||
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
|
||||
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
|
||||
{
|
||||
.name = "dce_0_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_0_1", .id = DSC_1,
|
||||
.base = 0x80000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2),
|
||||
.sblk = &dsc_sblk_1,
|
||||
}, {
|
||||
.name = "dce_1_0", .id = DSC_2,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_1_1", .id = DSC_3,
|
||||
.base = 0x81000, .len = 0x4,
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &dsc_sblk_1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg sm8550_intf[] = {
|
||||
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
|
||||
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
|
||||
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x300,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x36000, .len = 0x300,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x280,
|
||||
.features = INTF_SC7280_MASK,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
.intr_tear_rd_ptr = -1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8550_perf_data = {
|
||||
|
@ -224,11 +415,15 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
|
|||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version sm8550_mdss_ver = {
|
||||
.core_major_ver = 9,
|
||||
.core_minor_ver = 0,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_sm8550_cfg = {
|
||||
.mdss_ver = &sm8550_mdss_ver,
|
||||
.caps = &sm8550_dpu_caps,
|
||||
.ubwc = &sm8550_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sm8550_mdp),
|
||||
.mdp = sm8550_mdp,
|
||||
.mdp = &sm8550_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sm8550_ctl),
|
||||
.ctl = sm8550_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm8550_sspp),
|
||||
|
@ -245,18 +440,9 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
|
|||
.merge_3d = sm8550_merge_3d,
|
||||
.intf_count = ARRAY_SIZE(sm8550_intf),
|
||||
.intf = sm8550_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif_count = ARRAY_SIZE(sm8550_vbif),
|
||||
.vbif = sm8550_vbif,
|
||||
.perf = &sm8550_perf_data,
|
||||
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
|
||||
BIT(MDP_SSPP_TOP0_INTR2) | \
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
|
||||
BIT(MDP_INTF0_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_INTR) | \
|
||||
BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_INTR) | \
|
||||
BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
|
||||
BIT(MDP_INTF3_7xxx_INTR),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -33,11 +33,11 @@ enum dpu_perf_mode {
|
|||
|
||||
/**
|
||||
* _dpu_core_perf_calc_bw() - to calculate BW per crtc
|
||||
* @kms: pointer to the dpu_kms
|
||||
* @perf_cfg: performance configuration
|
||||
* @crtc: pointer to a crtc
|
||||
* Return: returns aggregated BW for all planes in crtc.
|
||||
*/
|
||||
static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
|
||||
static u64 _dpu_core_perf_calc_bw(const struct dpu_perf_cfg *perf_cfg,
|
||||
struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_plane *plane;
|
||||
|
@ -53,7 +53,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
|
|||
crtc_plane_bw += pstate->plane_fetch_bw;
|
||||
}
|
||||
|
||||
bw_factor = kms->catalog->perf->bw_inefficiency_factor;
|
||||
bw_factor = perf_cfg->bw_inefficiency_factor;
|
||||
if (bw_factor) {
|
||||
crtc_plane_bw *= bw_factor;
|
||||
do_div(crtc_plane_bw, 100);
|
||||
|
@ -64,12 +64,12 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
|
|||
|
||||
/**
|
||||
* _dpu_core_perf_calc_clk() - to calculate clock per crtc
|
||||
* @kms: pointer to the dpu_kms
|
||||
* @perf_cfg: performance configuration
|
||||
* @crtc: pointer to a crtc
|
||||
* @state: pointer to a crtc state
|
||||
* Return: returns max clk for all planes in crtc.
|
||||
*/
|
||||
static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
|
||||
static u64 _dpu_core_perf_calc_clk(const struct dpu_perf_cfg *perf_cfg,
|
||||
struct drm_crtc *crtc, struct drm_crtc_state *state)
|
||||
{
|
||||
struct drm_plane *plane;
|
||||
|
@ -90,7 +90,7 @@ static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
|
|||
crtc_clk = max(pstate->plane_clk, crtc_clk);
|
||||
}
|
||||
|
||||
clk_factor = kms->catalog->perf->clk_inefficiency_factor;
|
||||
clk_factor = perf_cfg->clk_inefficiency_factor;
|
||||
if (clk_factor) {
|
||||
crtc_clk *= clk_factor;
|
||||
do_div(crtc_clk, 100);
|
||||
|
@ -106,30 +106,32 @@ static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
|
|||
return to_dpu_kms(priv->kms);
|
||||
}
|
||||
|
||||
static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
|
||||
struct drm_crtc *crtc,
|
||||
struct drm_crtc_state *state,
|
||||
struct dpu_core_perf_params *perf)
|
||||
static void _dpu_core_perf_calc_crtc(const struct dpu_core_perf *core_perf,
|
||||
struct drm_crtc *crtc,
|
||||
struct drm_crtc_state *state,
|
||||
struct dpu_core_perf_params *perf)
|
||||
{
|
||||
if (!kms || !kms->catalog || !crtc || !state || !perf) {
|
||||
const struct dpu_perf_cfg *perf_cfg = core_perf->perf_cfg;
|
||||
|
||||
if (!perf_cfg || !crtc || !state || !perf) {
|
||||
DPU_ERROR("invalid parameters\n");
|
||||
return;
|
||||
}
|
||||
|
||||
memset(perf, 0, sizeof(struct dpu_core_perf_params));
|
||||
|
||||
if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
|
||||
if (core_perf->perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
|
||||
perf->bw_ctl = 0;
|
||||
perf->max_per_pipe_ib = 0;
|
||||
perf->core_clk_rate = 0;
|
||||
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
|
||||
perf->bw_ctl = kms->perf.fix_core_ab_vote;
|
||||
perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
|
||||
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
|
||||
} else if (core_perf->perf_tune.mode == DPU_PERF_MODE_FIXED) {
|
||||
perf->bw_ctl = core_perf->fix_core_ab_vote;
|
||||
perf->max_per_pipe_ib = core_perf->fix_core_ib_vote;
|
||||
perf->core_clk_rate = core_perf->fix_core_clk_rate;
|
||||
} else {
|
||||
perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
|
||||
perf->max_per_pipe_ib = kms->catalog->perf->min_dram_ib;
|
||||
perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
|
||||
perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, crtc);
|
||||
perf->max_per_pipe_ib = perf_cfg->min_dram_ib;
|
||||
perf->core_clk_rate = _dpu_core_perf_calc_clk(perf_cfg, crtc, state);
|
||||
}
|
||||
|
||||
DRM_DEBUG_ATOMIC(
|
||||
|
@ -154,10 +156,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
|
|||
}
|
||||
|
||||
kms = _dpu_crtc_get_kms(crtc);
|
||||
if (!kms->catalog) {
|
||||
DPU_ERROR("invalid parameters\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* we only need bandwidth check on real-time clients (interfaces) */
|
||||
if (dpu_crtc_get_client_type(crtc) == NRT_CLIENT)
|
||||
|
@ -166,30 +164,30 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
|
|||
dpu_cstate = to_dpu_crtc_state(state);
|
||||
|
||||
/* obtain new values */
|
||||
_dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf);
|
||||
_dpu_core_perf_calc_crtc(&kms->perf, crtc, state, &dpu_cstate->new_perf);
|
||||
|
||||
bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
|
||||
curr_client_type = dpu_crtc_get_client_type(crtc);
|
||||
|
||||
drm_for_each_crtc(tmp_crtc, crtc->dev) {
|
||||
if (tmp_crtc->enabled &&
|
||||
(dpu_crtc_get_client_type(tmp_crtc) ==
|
||||
curr_client_type) && (tmp_crtc != crtc)) {
|
||||
dpu_crtc_get_client_type(tmp_crtc) == curr_client_type &&
|
||||
tmp_crtc != crtc) {
|
||||
struct dpu_crtc_state *tmp_cstate =
|
||||
to_dpu_crtc_state(tmp_crtc->state);
|
||||
|
||||
DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n",
|
||||
tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
|
||||
tmp_cstate->bw_control);
|
||||
tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
|
||||
tmp_cstate->bw_control);
|
||||
|
||||
bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
|
||||
bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
|
||||
}
|
||||
|
||||
/* convert bandwidth to kb */
|
||||
bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
|
||||
DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
|
||||
|
||||
threshold = kms->catalog->perf->max_bw_high;
|
||||
threshold = kms->perf.perf_cfg->max_bw_high;
|
||||
|
||||
DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
|
||||
|
||||
|
@ -217,6 +215,9 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
|
|||
int i, ret = 0;
|
||||
u64 avg_bw;
|
||||
|
||||
if (!kms->num_paths)
|
||||
return 0;
|
||||
|
||||
drm_for_each_crtc(tmp_crtc, crtc->dev) {
|
||||
if (tmp_crtc->enabled &&
|
||||
curr_client_type ==
|
||||
|
@ -234,9 +235,6 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
|
|||
}
|
||||
}
|
||||
|
||||
if (!kms->num_paths)
|
||||
return 0;
|
||||
|
||||
avg_bw = perf.bw_ctl;
|
||||
do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/
|
||||
|
||||
|
@ -265,11 +263,6 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
|
|||
}
|
||||
|
||||
kms = _dpu_crtc_get_kms(crtc);
|
||||
if (!kms->catalog) {
|
||||
DPU_ERROR("invalid kms\n");
|
||||
return;
|
||||
}
|
||||
|
||||
dpu_crtc = to_dpu_crtc(crtc);
|
||||
|
||||
if (atomic_dec_return(&kms->bandwidth_ref) > 0)
|
||||
|
@ -286,30 +279,30 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
|
|||
|
||||
static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
|
||||
{
|
||||
u64 clk_rate = kms->perf.perf_tune.min_core_clk;
|
||||
u64 clk_rate;
|
||||
struct drm_crtc *crtc;
|
||||
struct dpu_crtc_state *dpu_cstate;
|
||||
|
||||
if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
|
||||
return kms->perf.fix_core_clk_rate;
|
||||
|
||||
if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM)
|
||||
return kms->perf.max_core_clk_rate;
|
||||
|
||||
clk_rate = 0;
|
||||
drm_for_each_crtc(crtc, kms->dev) {
|
||||
if (crtc->enabled) {
|
||||
dpu_cstate = to_dpu_crtc_state(crtc->state);
|
||||
clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
|
||||
clk_rate);
|
||||
clk_rate = clk_round_rate(kms->perf.core_clk,
|
||||
clk_rate);
|
||||
}
|
||||
}
|
||||
|
||||
if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
|
||||
clk_rate = kms->perf.fix_core_clk_rate;
|
||||
|
||||
DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
|
||||
|
||||
return clk_rate;
|
||||
}
|
||||
|
||||
int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
||||
int params_changed, bool stop_req)
|
||||
int params_changed)
|
||||
{
|
||||
struct dpu_core_perf_params *new, *old;
|
||||
bool update_bus = false, update_clk = false;
|
||||
|
@ -325,21 +318,17 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
|||
}
|
||||
|
||||
kms = _dpu_crtc_get_kms(crtc);
|
||||
if (!kms->catalog) {
|
||||
DPU_ERROR("invalid kms\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dpu_crtc = to_dpu_crtc(crtc);
|
||||
dpu_cstate = to_dpu_crtc_state(crtc->state);
|
||||
|
||||
DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n",
|
||||
crtc->base.id, stop_req, kms->perf.core_clk_rate);
|
||||
DRM_DEBUG_ATOMIC("crtc:%d enabled:%d core_clk:%llu\n",
|
||||
crtc->base.id, crtc->enabled, kms->perf.core_clk_rate);
|
||||
|
||||
old = &dpu_crtc->cur_perf;
|
||||
new = &dpu_cstate->new_perf;
|
||||
|
||||
if (crtc->enabled && !stop_req) {
|
||||
if (crtc->enabled) {
|
||||
/*
|
||||
* cases for bus bandwidth update.
|
||||
* 1. new bandwidth vote - "ab or ib vote" is higher
|
||||
|
@ -359,10 +348,8 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
|||
update_bus = true;
|
||||
}
|
||||
|
||||
if ((params_changed &&
|
||||
(new->core_clk_rate > old->core_clk_rate)) ||
|
||||
(!params_changed &&
|
||||
(new->core_clk_rate < old->core_clk_rate))) {
|
||||
if ((params_changed && new->core_clk_rate > old->core_clk_rate) ||
|
||||
(!params_changed && new->core_clk_rate < old->core_clk_rate)) {
|
||||
old->core_clk_rate = new->core_clk_rate;
|
||||
update_clk = true;
|
||||
}
|
||||
|
@ -374,7 +361,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
|||
}
|
||||
|
||||
trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl,
|
||||
new->core_clk_rate, stop_req, update_bus, update_clk);
|
||||
new->core_clk_rate, !crtc->enabled, update_bus, update_clk);
|
||||
|
||||
if (update_bus) {
|
||||
ret = _dpu_core_perf_crtc_update_bus(kms, crtc);
|
||||
|
@ -392,7 +379,9 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
|||
if (update_clk) {
|
||||
clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
|
||||
|
||||
trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);
|
||||
DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
|
||||
|
||||
trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate);
|
||||
|
||||
clk_rate = min(clk_rate, kms->perf.max_core_clk_rate);
|
||||
ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate);
|
||||
|
@ -413,7 +402,6 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file,
|
|||
const char __user *user_buf, size_t count, loff_t *ppos)
|
||||
{
|
||||
struct dpu_core_perf *perf = file->private_data;
|
||||
const struct dpu_perf_cfg *cfg = perf->catalog->perf;
|
||||
u32 perf_mode = 0;
|
||||
int ret;
|
||||
|
||||
|
@ -428,14 +416,9 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file,
|
|||
DRM_INFO("fix performance mode\n");
|
||||
} else if (perf_mode == DPU_PERF_MODE_MINIMUM) {
|
||||
/* run the driver with max clk and BW vote */
|
||||
perf->perf_tune.min_core_clk = perf->max_core_clk_rate;
|
||||
perf->perf_tune.min_bus_vote =
|
||||
(u64) cfg->max_bw_high * 1000;
|
||||
DRM_INFO("minimum performance mode\n");
|
||||
} else if (perf_mode == DPU_PERF_MODE_NORMAL) {
|
||||
/* reset the perf tune params to 0 */
|
||||
perf->perf_tune.min_core_clk = 0;
|
||||
perf->perf_tune.min_bus_vote = 0;
|
||||
DRM_INFO("normal performance mode\n");
|
||||
}
|
||||
perf->perf_tune.mode = perf_mode;
|
||||
|
@ -451,10 +434,8 @@ static ssize_t _dpu_core_perf_mode_read(struct file *file,
|
|||
char buf[128];
|
||||
|
||||
len = scnprintf(buf, sizeof(buf),
|
||||
"mode %d min_mdp_clk %llu min_bus_vote %llu\n",
|
||||
perf->perf_tune.mode,
|
||||
perf->perf_tune.min_core_clk,
|
||||
perf->perf_tune.min_bus_vote);
|
||||
"mode %d\n",
|
||||
perf->perf_tune.mode);
|
||||
|
||||
return simple_read_from_buffer(buff, count, ppos, buf, len);
|
||||
}
|
||||
|
@ -468,7 +449,6 @@ static const struct file_operations dpu_core_perf_mode_fops = {
|
|||
int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
|
||||
{
|
||||
struct dpu_core_perf *perf = &dpu_kms->perf;
|
||||
const struct dpu_mdss_cfg *catalog = perf->catalog;
|
||||
struct dentry *entry;
|
||||
|
||||
entry = debugfs_create_dir("core_perf", parent);
|
||||
|
@ -480,15 +460,15 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
|
|||
debugfs_create_u32("enable_bw_release", 0600, entry,
|
||||
(u32 *)&perf->enable_bw_release);
|
||||
debugfs_create_u32("threshold_low", 0600, entry,
|
||||
(u32 *)&catalog->perf->max_bw_low);
|
||||
(u32 *)&perf->perf_cfg->max_bw_low);
|
||||
debugfs_create_u32("threshold_high", 0600, entry,
|
||||
(u32 *)&catalog->perf->max_bw_high);
|
||||
(u32 *)&perf->perf_cfg->max_bw_high);
|
||||
debugfs_create_u32("min_core_ib", 0600, entry,
|
||||
(u32 *)&catalog->perf->min_core_ib);
|
||||
(u32 *)&perf->perf_cfg->min_core_ib);
|
||||
debugfs_create_u32("min_llcc_ib", 0600, entry,
|
||||
(u32 *)&catalog->perf->min_llcc_ib);
|
||||
(u32 *)&perf->perf_cfg->min_llcc_ib);
|
||||
debugfs_create_u32("min_dram_ib", 0600, entry,
|
||||
(u32 *)&catalog->perf->min_dram_ib);
|
||||
(u32 *)&perf->perf_cfg->min_dram_ib);
|
||||
debugfs_create_file("perf_mode", 0600, entry,
|
||||
(u32 *)perf, &dpu_core_perf_mode_fops);
|
||||
debugfs_create_u64("fix_core_clk_rate", 0600, entry,
|
||||
|
@ -502,33 +482,12 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
|
|||
}
|
||||
#endif
|
||||
|
||||
void dpu_core_perf_destroy(struct dpu_core_perf *perf)
|
||||
{
|
||||
if (!perf) {
|
||||
DPU_ERROR("invalid parameters\n");
|
||||
return;
|
||||
}
|
||||
|
||||
perf->max_core_clk_rate = 0;
|
||||
perf->core_clk = NULL;
|
||||
perf->catalog = NULL;
|
||||
perf->dev = NULL;
|
||||
}
|
||||
|
||||
int dpu_core_perf_init(struct dpu_core_perf *perf,
|
||||
struct drm_device *dev,
|
||||
const struct dpu_mdss_cfg *catalog,
|
||||
struct clk *core_clk)
|
||||
const struct dpu_perf_cfg *perf_cfg,
|
||||
unsigned long max_core_clk_rate)
|
||||
{
|
||||
perf->dev = dev;
|
||||
perf->catalog = catalog;
|
||||
perf->core_clk = core_clk;
|
||||
|
||||
perf->max_core_clk_rate = clk_get_rate(core_clk);
|
||||
if (!perf->max_core_clk_rate) {
|
||||
DPU_DEBUG("optional max core clk rate, use default\n");
|
||||
perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
|
||||
}
|
||||
perf->perf_cfg = perf_cfg;
|
||||
perf->max_core_clk_rate = max_core_clk_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -12,8 +12,6 @@
|
|||
|
||||
#include "dpu_hw_catalog.h"
|
||||
|
||||
#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
|
||||
|
||||
/**
|
||||
* struct dpu_core_perf_params - definition of performance parameters
|
||||
* @max_per_pipe_ib: maximum instantaneous bandwidth request
|
||||
|
@ -29,21 +27,14 @@ struct dpu_core_perf_params {
|
|||
/**
|
||||
* struct dpu_core_perf_tune - definition of performance tuning control
|
||||
* @mode: performance mode
|
||||
* @min_core_clk: minimum core clock
|
||||
* @min_bus_vote: minimum bus vote
|
||||
*/
|
||||
struct dpu_core_perf_tune {
|
||||
u32 mode;
|
||||
u64 min_core_clk;
|
||||
u64 min_bus_vote;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpu_core_perf - definition of core performance context
|
||||
* @dev: Pointer to drm device
|
||||
* @debugfs_root: top level debug folder
|
||||
* @catalog: Pointer to catalog configuration
|
||||
* @core_clk: Pointer to the core clock
|
||||
* @perf_cfg: Platform-specific performance configuration
|
||||
* @core_clk_rate: current core clock rate
|
||||
* @max_core_clk_rate: maximum allowable core clock rate
|
||||
* @perf_tune: debug control for performance tuning
|
||||
|
@ -53,10 +44,7 @@ struct dpu_core_perf_tune {
|
|||
* @fix_core_ab_vote: fixed core ab vote in bps used in mode 2
|
||||
*/
|
||||
struct dpu_core_perf {
|
||||
struct drm_device *dev;
|
||||
struct dentry *debugfs_root;
|
||||
const struct dpu_mdss_cfg *catalog;
|
||||
struct clk *core_clk;
|
||||
const struct dpu_perf_cfg *perf_cfg;
|
||||
u64 core_clk_rate;
|
||||
u64 max_core_clk_rate;
|
||||
struct dpu_core_perf_tune perf_tune;
|
||||
|
@ -79,11 +67,10 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
|
|||
* dpu_core_perf_crtc_update - update performance of the given crtc
|
||||
* @crtc: Pointer to crtc
|
||||
* @params_changed: true if crtc parameters are modified
|
||||
* @stop_req: true if this is a stop request
|
||||
* return: zero if success, or error code otherwise
|
||||
*/
|
||||
int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
||||
int params_changed, bool stop_req);
|
||||
int params_changed);
|
||||
|
||||
/**
|
||||
* dpu_core_perf_crtc_release_bw - release bandwidth of the given crtc
|
||||
|
@ -91,23 +78,15 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
|||
*/
|
||||
void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc);
|
||||
|
||||
/**
|
||||
* dpu_core_perf_destroy - destroy the given core performance context
|
||||
* @perf: Pointer to core performance context
|
||||
*/
|
||||
void dpu_core_perf_destroy(struct dpu_core_perf *perf);
|
||||
|
||||
/**
|
||||
* dpu_core_perf_init - initialize the given core performance context
|
||||
* @perf: Pointer to core performance context
|
||||
* @dev: Pointer to drm device
|
||||
* @catalog: Pointer to catalog
|
||||
* @core_clk: pointer to core clock
|
||||
* @perf_cfg: Pointer to platform performance configuration
|
||||
* @max_core_clk_rate: Maximum core clock rate
|
||||
*/
|
||||
int dpu_core_perf_init(struct dpu_core_perf *perf,
|
||||
struct drm_device *dev,
|
||||
const struct dpu_mdss_cfg *catalog,
|
||||
struct clk *core_clk);
|
||||
const struct dpu_perf_cfg *perf_cfg,
|
||||
unsigned long max_core_clk_rate);
|
||||
|
||||
struct dpu_kms;
|
||||
|
||||
|
|
|
@ -718,7 +718,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event)
|
|||
void dpu_crtc_complete_commit(struct drm_crtc *crtc)
|
||||
{
|
||||
trace_dpu_crtc_complete_commit(DRMID(crtc));
|
||||
dpu_core_perf_crtc_update(crtc, 0, false);
|
||||
dpu_core_perf_crtc_update(crtc, 0);
|
||||
_dpu_crtc_complete_flip(crtc);
|
||||
}
|
||||
|
||||
|
@ -884,7 +884,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
|
|||
return;
|
||||
|
||||
/* update performance setting before crtc kickoff */
|
||||
dpu_core_perf_crtc_update(crtc, 1, false);
|
||||
dpu_core_perf_crtc_update(crtc, 1);
|
||||
|
||||
/*
|
||||
* Final plane updates: Give each plane a chance to complete all
|
||||
|
@ -1100,7 +1100,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
|
|||
atomic_set(&dpu_crtc->frame_pending, 0);
|
||||
}
|
||||
|
||||
dpu_core_perf_crtc_update(crtc, 0, true);
|
||||
dpu_core_perf_crtc_update(crtc, 0);
|
||||
|
||||
drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
|
||||
dpu_encoder_register_frame_event_callback(encoder, NULL, NULL);
|
||||
|
|
|
@ -152,7 +152,6 @@ enum dpu_enc_rc_states {
|
|||
* @crtc_frame_event_cb_data: callback handler private data
|
||||
* @frame_done_timeout_ms: frame done timeout in ms
|
||||
* @frame_done_timer: watchdog timer for frame done event
|
||||
* @vsync_event_timer: vsync timer
|
||||
* @disp_info: local copy of msm_display_info struct
|
||||
* @idle_pc_supported: indicate if idle power collaps is supported
|
||||
* @rc_lock: resource control mutex lock to protect
|
||||
|
@ -160,7 +159,6 @@ enum dpu_enc_rc_states {
|
|||
* @rc_state: resource controller state
|
||||
* @delayed_off_work: delayed worker to schedule disabling of
|
||||
* clks and resources after IDLE_TIMEOUT time.
|
||||
* @vsync_event_work: worker to handle vsync event for autorefresh
|
||||
* @topology: topology of the display
|
||||
* @idle_timeout: idle timeout duration in milliseconds
|
||||
* @wide_bus_en: wide bus is enabled on this interface
|
||||
|
@ -194,7 +192,6 @@ struct dpu_encoder_virt {
|
|||
|
||||
atomic_t frame_done_timeout_ms;
|
||||
struct timer_list frame_done_timer;
|
||||
struct timer_list vsync_event_timer;
|
||||
|
||||
struct msm_display_info disp_info;
|
||||
|
||||
|
@ -202,7 +199,6 @@ struct dpu_encoder_virt {
|
|||
struct mutex rc_lock;
|
||||
enum dpu_enc_rc_states rc_state;
|
||||
struct delayed_work delayed_off_work;
|
||||
struct kthread_work vsync_event_work;
|
||||
struct msm_display_topology topology;
|
||||
|
||||
u32 idle_timeout;
|
||||
|
@ -543,11 +539,24 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
|
|||
return (num_dsc > 0) && (num_dsc > intf_count);
|
||||
}
|
||||
|
||||
static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
|
||||
{
|
||||
struct msm_drm_private *priv = drm_enc->dev->dev_private;
|
||||
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
|
||||
int index = dpu_enc->disp_info.h_tile_instance[0];
|
||||
|
||||
if (dpu_enc->disp_info.intf_type == INTF_DSI)
|
||||
return msm_dsi_get_dsc_config(priv->dsi[index]);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct msm_display_topology dpu_encoder_get_topology(
|
||||
struct dpu_encoder_virt *dpu_enc,
|
||||
struct dpu_kms *dpu_kms,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_crtc_state *crtc_state)
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_dsc_config *dsc)
|
||||
{
|
||||
struct msm_display_topology topology = {0};
|
||||
int i, intf_count = 0;
|
||||
|
@ -579,7 +588,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
|
|||
|
||||
topology.num_intf = intf_count;
|
||||
|
||||
if (dpu_enc->dsc) {
|
||||
if (dsc) {
|
||||
/*
|
||||
* In case of Display Stream Compression (DSC), we would use
|
||||
* 2 DSC encoders, 2 layer mixers and 1 interface
|
||||
|
@ -605,6 +614,7 @@ static int dpu_encoder_virt_atomic_check(
|
|||
struct drm_display_mode *adj_mode;
|
||||
struct msm_display_topology topology;
|
||||
struct dpu_global_state *global_state;
|
||||
struct drm_dsc_config *dsc;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
|
@ -640,7 +650,9 @@ static int dpu_encoder_virt_atomic_check(
|
|||
}
|
||||
}
|
||||
|
||||
topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state);
|
||||
dsc = dpu_encoder_get_dsc_config(drm_enc);
|
||||
|
||||
topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc);
|
||||
|
||||
/*
|
||||
* Release and Allocate resources on every modeset
|
||||
|
@ -1072,14 +1084,12 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
|
|||
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
|
||||
: NULL;
|
||||
|
||||
if (dpu_enc->dsc) {
|
||||
num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
|
||||
drm_enc->base.id, DPU_HW_BLK_DSC,
|
||||
hw_dsc, ARRAY_SIZE(hw_dsc));
|
||||
for (i = 0; i < num_dsc; i++) {
|
||||
dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
|
||||
dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
|
||||
}
|
||||
num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
|
||||
drm_enc->base.id, DPU_HW_BLK_DSC,
|
||||
hw_dsc, ARRAY_SIZE(hw_dsc));
|
||||
for (i = 0; i < num_dsc; i++) {
|
||||
dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
|
||||
dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
|
||||
}
|
||||
|
||||
dpu_enc->dsc_mask = dsc_mask;
|
||||
|
@ -1187,6 +1197,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
|
|||
|
||||
dpu_enc = to_dpu_encoder_virt(drm_enc);
|
||||
|
||||
dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
|
||||
|
||||
mutex_lock(&dpu_enc->enc_lock);
|
||||
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
|
||||
|
||||
|
@ -1754,49 +1766,6 @@ int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void dpu_encoder_vsync_event_handler(struct timer_list *t)
|
||||
{
|
||||
struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
|
||||
vsync_event_timer);
|
||||
struct drm_encoder *drm_enc = &dpu_enc->base;
|
||||
struct msm_drm_private *priv;
|
||||
struct msm_drm_thread *event_thread;
|
||||
|
||||
if (!drm_enc->dev || !drm_enc->crtc) {
|
||||
DPU_ERROR("invalid parameters\n");
|
||||
return;
|
||||
}
|
||||
|
||||
priv = drm_enc->dev->dev_private;
|
||||
|
||||
if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
|
||||
DPU_ERROR("invalid crtc index\n");
|
||||
return;
|
||||
}
|
||||
event_thread = &priv->event_thread[drm_enc->crtc->index];
|
||||
if (!event_thread) {
|
||||
DPU_ERROR("event_thread not found for crtc:%d\n",
|
||||
drm_enc->crtc->index);
|
||||
return;
|
||||
}
|
||||
|
||||
del_timer(&dpu_enc->vsync_event_timer);
|
||||
}
|
||||
|
||||
static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
|
||||
{
|
||||
struct dpu_encoder_virt *dpu_enc = container_of(work,
|
||||
struct dpu_encoder_virt, vsync_event_work);
|
||||
ktime_t wakeup_time;
|
||||
|
||||
if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
|
||||
return;
|
||||
|
||||
trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
|
||||
mod_timer(&dpu_enc->vsync_event_timer,
|
||||
nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
|
||||
}
|
||||
|
||||
static u32
|
||||
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
|
||||
u32 enc_ip_width)
|
||||
|
@ -1956,7 +1925,6 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
|
|||
{
|
||||
struct dpu_encoder_virt *dpu_enc;
|
||||
struct dpu_encoder_phys *phys;
|
||||
ktime_t wakeup_time;
|
||||
unsigned long timeout_ms;
|
||||
unsigned int i;
|
||||
|
||||
|
@ -1982,14 +1950,6 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
|
|||
phys->ops.handle_post_kickoff(phys);
|
||||
}
|
||||
|
||||
if (dpu_enc->disp_info.intf_type == INTF_DSI &&
|
||||
!dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
|
||||
trace_dpu_enc_early_kickoff(DRMID(drm_enc),
|
||||
ktime_to_ms(wakeup_time));
|
||||
mod_timer(&dpu_enc->vsync_event_timer,
|
||||
nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
|
||||
}
|
||||
|
||||
DPU_ATRACE_END("encoder_kickoff");
|
||||
}
|
||||
|
||||
|
@ -2108,8 +2068,10 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
|
|||
phys_enc->hw_pp->merge_3d->idx);
|
||||
}
|
||||
|
||||
if (dpu_enc->dsc)
|
||||
if (dpu_enc->dsc) {
|
||||
dpu_encoder_unprep_dsc(dpu_enc);
|
||||
dpu_enc->dsc = NULL;
|
||||
}
|
||||
|
||||
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
|
||||
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
|
||||
|
@ -2290,8 +2252,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
|
|||
dpu_enc->idle_pc_supported =
|
||||
dpu_kms->catalog->caps->has_idle_pc;
|
||||
|
||||
dpu_enc->dsc = disp_info->dsc;
|
||||
|
||||
mutex_lock(&dpu_enc->enc_lock);
|
||||
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
|
||||
/*
|
||||
|
@ -2423,11 +2383,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
|
|||
timer_setup(&dpu_enc->frame_done_timer,
|
||||
dpu_encoder_frame_done_timeout, 0);
|
||||
|
||||
if (disp_info->intf_type == INTF_DSI)
|
||||
timer_setup(&dpu_enc->vsync_event_timer,
|
||||
dpu_encoder_vsync_event_handler,
|
||||
0);
|
||||
else if (disp_info->intf_type == INTF_DP)
|
||||
if (disp_info->intf_type == INTF_DP)
|
||||
dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
|
||||
priv->dp[disp_info->h_tile_instance[0]]);
|
||||
|
||||
|
@ -2435,9 +2391,6 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
|
|||
dpu_encoder_off_work);
|
||||
dpu_enc->idle_timeout = IDLE_TIMEOUT;
|
||||
|
||||
kthread_init_work(&dpu_enc->vsync_event_work,
|
||||
dpu_encoder_vsync_event_work_handler);
|
||||
|
||||
memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
|
||||
|
||||
DPU_DEBUG_ENC(dpu_enc, "created\n");
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
* @is_cmd_mode Boolean to indicate if the CMD mode is requested
|
||||
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
|
||||
* used instead of panel TE in cmd mode panels
|
||||
* @dsc: DSC configuration data for DSC-enabled displays
|
||||
*/
|
||||
struct msm_display_info {
|
||||
enum dpu_intf_type intf_type;
|
||||
|
@ -36,7 +35,6 @@ struct msm_display_info {
|
|||
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
|
||||
bool is_cmd_mode;
|
||||
bool is_te_using_watchdog_timer;
|
||||
struct drm_dsc_config *dsc;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
|
|||
to_dpu_encoder_phys_cmd(phys_enc);
|
||||
struct dpu_hw_ctl *ctl;
|
||||
struct dpu_hw_intf_cfg intf_cfg = { 0 };
|
||||
struct dpu_hw_intf_cmd_mode_cfg cmd_mode_cfg = {};
|
||||
|
||||
ctl = phys_enc->hw_ctl;
|
||||
if (!ctl->ops.setup_intf_cfg)
|
||||
|
@ -68,8 +69,11 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
|
|||
phys_enc->hw_intf,
|
||||
phys_enc->hw_pp->idx);
|
||||
|
||||
if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
|
||||
phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
|
||||
if (intf_cfg.dsc != 0)
|
||||
cmd_mode_cfg.data_compress = true;
|
||||
|
||||
if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)
|
||||
phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg);
|
||||
}
|
||||
|
||||
static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
|
||||
|
|
|
@ -40,7 +40,7 @@ static bool dpu_encoder_phys_vid_is_master(
|
|||
static void drm_mode_to_intf_timing_params(
|
||||
const struct dpu_encoder_phys *phys_enc,
|
||||
const struct drm_display_mode *mode,
|
||||
struct intf_timing_params *timing)
|
||||
struct dpu_hw_intf_timing_params *timing)
|
||||
{
|
||||
memset(timing, 0, sizeof(*timing));
|
||||
|
||||
|
@ -114,7 +114,7 @@ static void drm_mode_to_intf_timing_params(
|
|||
}
|
||||
}
|
||||
|
||||
static u32 get_horizontal_total(const struct intf_timing_params *timing)
|
||||
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
|
||||
{
|
||||
u32 active = timing->xres;
|
||||
u32 inactive =
|
||||
|
@ -123,7 +123,7 @@ static u32 get_horizontal_total(const struct intf_timing_params *timing)
|
|||
return active + inactive;
|
||||
}
|
||||
|
||||
static u32 get_vertical_total(const struct intf_timing_params *timing)
|
||||
static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
|
||||
{
|
||||
u32 active = timing->yres;
|
||||
u32 inactive =
|
||||
|
@ -148,7 +148,7 @@ static u32 get_vertical_total(const struct intf_timing_params *timing)
|
|||
*/
|
||||
static u32 programmable_fetch_get_num_lines(
|
||||
struct dpu_encoder_phys *phys_enc,
|
||||
const struct intf_timing_params *timing)
|
||||
const struct dpu_hw_intf_timing_params *timing)
|
||||
{
|
||||
u32 worst_case_needed_lines =
|
||||
phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
|
||||
|
@ -196,9 +196,9 @@ static u32 programmable_fetch_get_num_lines(
|
|||
* @timing: Pointer to the intf timing information for the requested mode
|
||||
*/
|
||||
static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
|
||||
const struct intf_timing_params *timing)
|
||||
const struct dpu_hw_intf_timing_params *timing)
|
||||
{
|
||||
struct intf_prog_fetch f = { 0 };
|
||||
struct dpu_hw_intf_prog_fetch f = { 0 };
|
||||
u32 vfp_fetch_lines = 0;
|
||||
u32 horiz_total = 0;
|
||||
u32 vert_total = 0;
|
||||
|
@ -231,7 +231,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
|
|||
struct dpu_encoder_phys *phys_enc)
|
||||
{
|
||||
struct drm_display_mode mode;
|
||||
struct intf_timing_params timing_params = { 0 };
|
||||
struct dpu_hw_intf_timing_params timing_params = { 0 };
|
||||
const struct dpu_format *fmt = NULL;
|
||||
u32 fmt_fourcc = DRM_FORMAT_RGB888;
|
||||
unsigned long lock_flags;
|
||||
|
@ -522,7 +522,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
|
|||
{
|
||||
unsigned long lock_flags;
|
||||
int ret;
|
||||
struct intf_status intf_status = {0};
|
||||
struct dpu_hw_intf_status intf_status = {0};
|
||||
|
||||
if (!phys_enc->parent || !phys_enc->parent->dev) {
|
||||
DPU_ERROR("invalid encoder/device\n");
|
||||
|
@ -651,7 +651,7 @@ static int dpu_encoder_phys_vid_get_line_count(
|
|||
static int dpu_encoder_phys_vid_get_frame_count(
|
||||
struct dpu_encoder_phys *phys_enc)
|
||||
{
|
||||
struct intf_status s = {0};
|
||||
struct dpu_hw_intf_status s = {0};
|
||||
u32 fetch_start = 0;
|
||||
struct drm_display_mode mode;
|
||||
|
||||
|
|
|
@ -446,7 +446,8 @@ static int dpu_encoder_phys_wb_wait_for_commit_done(
|
|||
wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
|
||||
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
|
||||
|
||||
ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE,
|
||||
ret = dpu_encoder_helper_wait_for_irq(phys_enc,
|
||||
phys_enc->irq[INTR_IDX_WB_DONE],
|
||||
dpu_encoder_phys_wb_done_irq, &wait_info);
|
||||
if (ret == -ETIMEDOUT)
|
||||
_dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
|
||||
|
|
|
@ -33,6 +33,9 @@
|
|||
#define VIG_SC7180_MASK \
|
||||
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
|
||||
|
||||
#define VIG_SM6125_MASK \
|
||||
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
|
||||
|
||||
#define VIG_SC7180_MASK_SDMA \
|
||||
(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
|
||||
|
||||
|
@ -93,19 +96,15 @@
|
|||
#define CTL_SM8550_MASK \
|
||||
(CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
|
||||
|
||||
#define MERGE_3D_SM8150_MASK (0)
|
||||
|
||||
#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
|
||||
|
||||
#define INTF_SDM845_MASK (0)
|
||||
|
||||
#define INTF_SC7180_MASK \
|
||||
(BIT(DPU_INTF_INPUT_CTRL) | \
|
||||
BIT(DPU_INTF_TE) | \
|
||||
BIT(DPU_INTF_STATUS_SUPPORTED) | \
|
||||
BIT(DPU_DATA_HCTL_EN))
|
||||
|
||||
#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS))
|
||||
#define INTF_SC7280_MASK (INTF_SC7180_MASK)
|
||||
|
||||
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
|
||||
BIT(DPU_WB_UBWC) | \
|
||||
|
@ -252,15 +251,15 @@ static const uint32_t wb2_formats[] = {
|
|||
*************************************************************/
|
||||
|
||||
/* SSPP common configuration */
|
||||
#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
|
||||
#define _VIG_SBLK(sdma_pri, qseed_ver) \
|
||||
{ \
|
||||
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
|
||||
.maxupscale = MAX_UPSCALE_RATIO, \
|
||||
.smart_dma_priority = sdma_pri, \
|
||||
.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
|
||||
.scaler_blk = {.name = "scaler", \
|
||||
.id = qseed_ver, \
|
||||
.base = 0xa00, .len = 0xa0,}, \
|
||||
.csc_blk = {.name = STRCAT("sspp_csc", num), \
|
||||
.csc_blk = {.name = "csc", \
|
||||
.id = DPU_SSPP_CSC_10BIT, \
|
||||
.base = 0x1a00, .len = 0x100,}, \
|
||||
.format_list = plane_formats_yuv, \
|
||||
|
@ -270,15 +269,15 @@ static const uint32_t wb2_formats[] = {
|
|||
.rotation_cfg = NULL, \
|
||||
}
|
||||
|
||||
#define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \
|
||||
#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \
|
||||
{ \
|
||||
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
|
||||
.maxupscale = MAX_UPSCALE_RATIO, \
|
||||
.smart_dma_priority = sdma_pri, \
|
||||
.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
|
||||
.scaler_blk = {.name = "scaler", \
|
||||
.id = qseed_ver, \
|
||||
.base = 0xa00, .len = 0xa0,}, \
|
||||
.csc_blk = {.name = STRCAT("sspp_csc", num), \
|
||||
.csc_blk = {.name = "csc", \
|
||||
.id = DPU_SSPP_CSC_10BIT, \
|
||||
.base = 0x1a00, .len = 0x100,}, \
|
||||
.format_list = plane_formats_yuv, \
|
||||
|
@ -288,7 +287,7 @@ static const uint32_t wb2_formats[] = {
|
|||
.rotation_cfg = rot_cfg, \
|
||||
}
|
||||
|
||||
#define _DMA_SBLK(num, sdma_pri) \
|
||||
#define _DMA_SBLK(sdma_pri) \
|
||||
{ \
|
||||
.maxdwnscale = SSPP_UNITY_SCALE, \
|
||||
.maxupscale = SSPP_UNITY_SCALE, \
|
||||
|
@ -300,13 +299,13 @@ static const uint32_t wb2_formats[] = {
|
|||
}
|
||||
|
||||
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
|
||||
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
|
||||
_VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
|
||||
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
|
||||
_VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
|
||||
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
|
||||
_VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
|
||||
|
||||
static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
|
||||
.rot_maxheight = 1088,
|
||||
|
@ -315,61 +314,52 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
|
|||
};
|
||||
|
||||
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3);
|
||||
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
|
||||
_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3);
|
||||
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
|
||||
_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3);
|
||||
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
|
||||
_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
|
||||
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
|
||||
|
||||
#define SSPP_BLK(_name, _id, _base, _len, _features, \
|
||||
_sblk, _xinid, _type, _clkctrl) \
|
||||
{ \
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = _len, \
|
||||
.features = _features, \
|
||||
.sblk = &_sblk, \
|
||||
.xin_id = _xinid, \
|
||||
.type = _type, \
|
||||
.clk_ctrl = _clkctrl \
|
||||
}
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1);
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2);
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3);
|
||||
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
|
||||
_VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
|
||||
_VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
|
||||
_VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
|
||||
_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
|
||||
_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
|
||||
_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4);
|
||||
|
||||
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
|
||||
_VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
|
||||
_VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4);
|
||||
_VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
|
||||
_VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
|
||||
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6);
|
||||
_VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4);
|
||||
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5);
|
||||
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6);
|
||||
|
||||
#define _VIG_SBLK_NOSCALE(num, sdma_pri) \
|
||||
#define _VIG_SBLK_NOSCALE(sdma_pri) \
|
||||
{ \
|
||||
.maxdwnscale = SSPP_UNITY_SCALE, \
|
||||
.maxupscale = SSPP_UNITY_SCALE, \
|
||||
|
@ -380,24 +370,13 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6);
|
|||
.virt_num_formats = ARRAY_SIZE(plane_formats), \
|
||||
}
|
||||
|
||||
static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
|
||||
static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
|
||||
static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2);
|
||||
static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1);
|
||||
|
||||
/*************************************************************
|
||||
* MIXER sub blocks config
|
||||
*************************************************************/
|
||||
|
||||
#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
|
||||
{ \
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0x320, \
|
||||
.features = _fmask, \
|
||||
.sblk = _sblk, \
|
||||
.pingpong = _pp, \
|
||||
.lm_pair_mask = (1 << _lmpair), \
|
||||
.dspp = _dspp \
|
||||
}
|
||||
|
||||
/* MSM8998 */
|
||||
|
||||
static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
|
||||
|
@ -444,151 +423,48 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
|
|||
* DSPP sub blocks config
|
||||
*************************************************************/
|
||||
static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
|
||||
.pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
|
||||
.pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700,
|
||||
.len = 0x90, .version = 0x10007},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
|
||||
.pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
|
||||
static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
|
||||
.pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700,
|
||||
.len = 0x90, .version = 0x40000},
|
||||
};
|
||||
|
||||
#define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0x1800, \
|
||||
.features = _mask, \
|
||||
.sblk = _sblk \
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* PINGPONG sub blocks config
|
||||
*************************************************************/
|
||||
static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
|
||||
.te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
|
||||
.te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
|
||||
.version = 0x1},
|
||||
.dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
|
||||
.dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0,
|
||||
.len = 0x20, .version = 0x10000},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
|
||||
.dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
|
||||
.dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0,
|
||||
.len = 0x20, .version = 0x10000},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
|
||||
.dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
|
||||
.dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0,
|
||||
.len = 0x20, .version = 0x20000},
|
||||
};
|
||||
|
||||
#define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0, \
|
||||
.features = BIT(DPU_PINGPONG_DITHER), \
|
||||
.merge_3d = _merge_3d, \
|
||||
.sblk = &_sblk, \
|
||||
.intr_done = _done, \
|
||||
.intr_rdptr = _rdptr, \
|
||||
}
|
||||
#define PP_BLK(_name, _id, _base, _features, _merge_3d, _sblk, _done, _rdptr) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0xd4, \
|
||||
.features = _features, \
|
||||
.merge_3d = _merge_3d, \
|
||||
.sblk = &_sblk, \
|
||||
.intr_done = _done, \
|
||||
.intr_rdptr = _rdptr, \
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* MERGE_3D sub blocks config
|
||||
*************************************************************/
|
||||
#define MERGE_3D_BLK(_name, _id, _base) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0x8, \
|
||||
.features = MERGE_3D_SM8150_MASK, \
|
||||
.sblk = NULL \
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* DSC sub blocks config
|
||||
*************************************************************/
|
||||
static const struct dpu_dsc_sub_blks dsc_sblk_0 = {
|
||||
.enc = {.base = 0x100, .len = 0x100},
|
||||
.ctl = {.base = 0xF00, .len = 0x10},
|
||||
.enc = {.name = "enc", .base = 0x100, .len = 0x9c},
|
||||
.ctl = {.name = "ctl", .base = 0xF00, .len = 0x10},
|
||||
};
|
||||
|
||||
static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
|
||||
.enc = {.base = 0x200, .len = 0x100},
|
||||
.ctl = {.base = 0xF80, .len = 0x10},
|
||||
.enc = {.name = "enc", .base = 0x200, .len = 0x9c},
|
||||
.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
|
||||
};
|
||||
|
||||
#define DSC_BLK(_name, _id, _base, _features) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0x140, \
|
||||
.features = _features, \
|
||||
}
|
||||
|
||||
#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = _len, \
|
||||
.features = BIT(DPU_DSC_HW_REV_1_2) | _features, \
|
||||
.sblk = &_sblk, \
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* INTF sub blocks config
|
||||
*************************************************************/
|
||||
#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = _len, \
|
||||
.features = _features, \
|
||||
.type = _type, \
|
||||
.controller_id = _ctrl_id, \
|
||||
.prog_fetch_lines_worst_case = _progfetch, \
|
||||
.intr_underrun = _underrun, \
|
||||
.intr_vsync = _vsync, \
|
||||
.intr_tear_rd_ptr = -1, \
|
||||
}
|
||||
|
||||
/* DSI Interface sub-block with TEAR registers (since DPU 5.0.0) */
|
||||
#define INTF_BLK_DSI_TE(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync, _tear_rd_ptr) \
|
||||
{\
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = _len, \
|
||||
.features = _features, \
|
||||
.type = _type, \
|
||||
.controller_id = _ctrl_id, \
|
||||
.prog_fetch_lines_worst_case = _progfetch, \
|
||||
.intr_underrun = _underrun, \
|
||||
.intr_vsync = _vsync, \
|
||||
.intr_tear_rd_ptr = _tear_rd_ptr, \
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* Writeback blocks config
|
||||
*************************************************************/
|
||||
#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
|
||||
__xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
|
||||
{ \
|
||||
.name = _name, .id = _id, \
|
||||
.base = _base, .len = 0x2c8, \
|
||||
.features = _features, \
|
||||
.format_list = wb2_formats, \
|
||||
.num_formats = ARRAY_SIZE(wb2_formats), \
|
||||
.clk_ctrl = _clk_ctrl, \
|
||||
.xin_id = __xin_id, \
|
||||
.vbif_idx = vbif_id, \
|
||||
.maxlinewidth = _max_linewidth, \
|
||||
.intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* VBIF sub blocks config
|
||||
*************************************************************/
|
||||
|
@ -663,6 +539,26 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct dpu_vbif_cfg sm8550_vbif[] = {
|
||||
{
|
||||
.name = "vbif_rt", .id = VBIF_RT,
|
||||
.base = 0, .len = 0x1040,
|
||||
.features = BIT(DPU_VBIF_QOS_REMAP),
|
||||
.xin_halt_timeout = 0x4000,
|
||||
.qos_rp_remap_size = 0x40,
|
||||
.qos_rt_tbl = {
|
||||
.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
|
||||
.priority_lvl = sdm845_rt_pri_lvl,
|
||||
},
|
||||
.qos_nrt_tbl = {
|
||||
.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
|
||||
.priority_lvl = sdm845_nrt_pri_lvl,
|
||||
},
|
||||
.memtype_count = 16,
|
||||
.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
|
||||
},
|
||||
};
|
||||
|
||||
/*************************************************************
|
||||
* PERF data config
|
||||
*************************************************************/
|
||||
|
@ -762,6 +658,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
|
|||
|
||||
#include "catalog/dpu_5_0_sm8150.h"
|
||||
#include "catalog/dpu_5_1_sc8180x.h"
|
||||
#include "catalog/dpu_5_4_sm6125.h"
|
||||
|
||||
#include "catalog/dpu_6_0_sm8250.h"
|
||||
#include "catalog/dpu_6_2_sc7180.h"
|
||||
|
|
|
@ -28,24 +28,10 @@
|
|||
|
||||
#define MAX_XIN_COUNT 16
|
||||
|
||||
/**
|
||||
* Supported UBWC feature versions
|
||||
*/
|
||||
enum {
|
||||
DPU_HW_UBWC_VER_10 = 0x100,
|
||||
DPU_HW_UBWC_VER_20 = 0x200,
|
||||
DPU_HW_UBWC_VER_30 = 0x300,
|
||||
DPU_HW_UBWC_VER_40 = 0x400,
|
||||
};
|
||||
|
||||
/**
|
||||
* MDP TOP BLOCK features
|
||||
* @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe
|
||||
* @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
|
||||
* @DPU_MDP_BWC, MDSS HW supports Bandwidth compression.
|
||||
* @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
|
||||
* compression initial revision
|
||||
* @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
|
||||
* @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
|
||||
* in a failure
|
||||
* @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register
|
||||
|
@ -56,9 +42,6 @@ enum {
|
|||
enum {
|
||||
DPU_MDP_PANIC_PER_PIPE = 0x1,
|
||||
DPU_MDP_10BIT_SUPPORT,
|
||||
DPU_MDP_BWC,
|
||||
DPU_MDP_UBWC_1_0,
|
||||
DPU_MDP_UBWC_1_5,
|
||||
DPU_MDP_AUDIO_SELECT,
|
||||
DPU_MDP_PERIPH_0_REMOVED,
|
||||
DPU_MDP_VSYNC_SEL,
|
||||
|
@ -181,7 +164,6 @@ enum {
|
|||
* @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
|
||||
* than video timing
|
||||
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
|
||||
* @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register
|
||||
* @DPU_INTF_MAX
|
||||
*/
|
||||
enum {
|
||||
|
@ -189,7 +171,6 @@ enum {
|
|||
DPU_INTF_TE,
|
||||
DPU_DATA_HCTL_EN,
|
||||
DPU_INTF_STATUS_SUPPORTED,
|
||||
DPU_INTF_DATA_COMPRESS,
|
||||
DPU_INTF_MAX
|
||||
};
|
||||
|
||||
|
@ -505,19 +486,6 @@ struct dpu_mdp_cfg {
|
|||
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpu_ubwc_cfg - UBWC and memory configuration
|
||||
*
|
||||
* @ubwc_version UBWC feature version (0x0 for not supported)
|
||||
* @highest_bank_bit: UBWC parameter
|
||||
* @ubwc_swizzle: ubwc default swizzle setting
|
||||
*/
|
||||
struct dpu_ubwc_cfg {
|
||||
u32 ubwc_version;
|
||||
u32 highest_bank_bit;
|
||||
u32 ubwc_swizzle;
|
||||
};
|
||||
|
||||
/* struct dpu_ctl_cfg : MDP CTL instance info
|
||||
* @id: index identifying this block
|
||||
* @base: register base offset to mdss
|
||||
|
@ -554,14 +522,14 @@ struct dpu_sspp_cfg {
|
|||
* @features bit mask identifying sub-blocks/features
|
||||
* @sblk: LM Sub-blocks information
|
||||
* @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported
|
||||
* @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
|
||||
* @lm_pair: ID of LM that can be controlled by same CTL
|
||||
*/
|
||||
struct dpu_lm_cfg {
|
||||
DPU_HW_BLK_INFO;
|
||||
const struct dpu_lm_sub_blks *sblk;
|
||||
u32 pingpong;
|
||||
u32 dspp;
|
||||
unsigned long lm_pair_mask;
|
||||
unsigned long lm_pair;
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -746,6 +714,16 @@ struct dpu_perf_cdp_cfg {
|
|||
bool wr_enable;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpu_mdss_version - DPU's major and minor versions
|
||||
* @core_major_ver: DPU core's major version
|
||||
* @core_minor_ver: DPU core's minor version
|
||||
*/
|
||||
struct dpu_mdss_version {
|
||||
u8 core_major_ver;
|
||||
u8 core_minor_ver;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpu_perf_cfg - performance control settings
|
||||
* @max_bw_low low threshold of maximum bandwidth (kbps)
|
||||
|
@ -796,20 +774,19 @@ struct dpu_perf_cfg {
|
|||
/**
|
||||
* struct dpu_mdss_cfg - information of MDSS HW
|
||||
* This is the main catalog data structure representing
|
||||
* this HW version. Contains number of instances,
|
||||
* register offsets, capabilities of the all MDSS HW sub-blocks.
|
||||
* this HW version. Contains dpu's major and minor versions,
|
||||
* number of instances, register offsets, capabilities of the
|
||||
* all MDSS HW sub-blocks.
|
||||
*
|
||||
* @dma_formats Supported formats for dma pipe
|
||||
* @cursor_formats Supported formats for cursor pipe
|
||||
* @vig_formats Supported formats for vig pipe
|
||||
* @mdss_irqs: Bitmap with the irqs supported by the target
|
||||
*/
|
||||
struct dpu_mdss_cfg {
|
||||
const struct dpu_mdss_version *mdss_ver;
|
||||
|
||||
const struct dpu_caps *caps;
|
||||
|
||||
const struct dpu_ubwc_cfg *ubwc;
|
||||
|
||||
u32 mdp_count;
|
||||
const struct dpu_mdp_cfg *mdp;
|
||||
|
||||
u32 ctl_count;
|
||||
|
@ -850,8 +827,6 @@ struct dpu_mdss_cfg {
|
|||
const struct dpu_format_extended *dma_formats;
|
||||
const struct dpu_format_extended *cursor_formats;
|
||||
const struct dpu_format_extended *vig_formats;
|
||||
|
||||
unsigned long mdss_irqs;
|
||||
};
|
||||
|
||||
extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
|
||||
|
@ -861,6 +836,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
|
|||
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
|
||||
|
|
|
@ -51,11 +51,9 @@ struct dpu_intr_reg {
|
|||
};
|
||||
|
||||
/*
|
||||
* struct dpu_intr_reg - List of DPU interrupt registers
|
||||
*
|
||||
* When making changes be sure to sync with dpu_hw_intr_reg
|
||||
* dpu_intr_set_legacy - List of DPU interrupt registers for DPU <= 6.x
|
||||
*/
|
||||
static const struct dpu_intr_reg dpu_intr_set[] = {
|
||||
static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
|
||||
[MDP_SSPP_TOP0_INTR] = {
|
||||
INTR_CLEAR,
|
||||
INTR_EN,
|
||||
|
@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
|
|||
MDP_AD4_INTR_EN_OFF(1),
|
||||
MDP_AD4_INTR_STATUS_OFF(1),
|
||||
},
|
||||
[MDP_INTF0_7xxx_INTR] = {
|
||||
};
|
||||
|
||||
/*
|
||||
* dpu_intr_set_7xxx - List of DPU interrupt registers for DPU >= 7.0
|
||||
*/
|
||||
static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
|
||||
[MDP_SSPP_TOP0_INTR] = {
|
||||
INTR_CLEAR,
|
||||
INTR_EN,
|
||||
INTR_STATUS
|
||||
},
|
||||
[MDP_SSPP_TOP0_INTR2] = {
|
||||
INTR2_CLEAR,
|
||||
INTR2_EN,
|
||||
INTR2_STATUS
|
||||
},
|
||||
[MDP_SSPP_TOP0_HIST_INTR] = {
|
||||
HIST_INTR_CLEAR,
|
||||
HIST_INTR_EN,
|
||||
HIST_INTR_STATUS
|
||||
},
|
||||
[MDP_INTF0_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(0),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(0),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(0)
|
||||
},
|
||||
[MDP_INTF1_7xxx_INTR] = {
|
||||
[MDP_INTF1_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(1),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(1),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(1)
|
||||
},
|
||||
[MDP_INTF1_7xxx_TEAR_INTR] = {
|
||||
[MDP_INTF1_TEAR_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
|
||||
MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
|
||||
MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
|
||||
},
|
||||
[MDP_INTF2_7xxx_INTR] = {
|
||||
[MDP_INTF2_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(2),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(2),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(2)
|
||||
},
|
||||
[MDP_INTF2_7xxx_TEAR_INTR] = {
|
||||
[MDP_INTF2_TEAR_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
|
||||
MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
|
||||
MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
|
||||
},
|
||||
[MDP_INTF3_7xxx_INTR] = {
|
||||
[MDP_INTF3_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(3),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(3),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(3)
|
||||
},
|
||||
[MDP_INTF4_7xxx_INTR] = {
|
||||
[MDP_INTF4_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(4),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(4),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(4)
|
||||
},
|
||||
[MDP_INTF5_7xxx_INTR] = {
|
||||
[MDP_INTF5_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(5),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(5),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(5)
|
||||
},
|
||||
[MDP_INTF6_7xxx_INTR] = {
|
||||
[MDP_INTF6_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(6),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(6),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(6)
|
||||
},
|
||||
[MDP_INTF7_7xxx_INTR] = {
|
||||
[MDP_INTF7_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(7),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(7),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(7)
|
||||
},
|
||||
[MDP_INTF8_7xxx_INTR] = {
|
||||
[MDP_INTF8_INTR] = {
|
||||
MDP_INTF_REV_7xxx_INTR_CLEAR(8),
|
||||
MDP_INTF_REV_7xxx_INTR_EN(8),
|
||||
MDP_INTF_REV_7xxx_INTR_STATUS(8)
|
||||
|
@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
|
|||
return IRQ_NONE;
|
||||
|
||||
spin_lock_irqsave(&intr->irq_lock, irq_flags);
|
||||
for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
|
||||
for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
|
||||
if (!test_bit(reg_idx, &intr->irq_mask))
|
||||
continue;
|
||||
|
||||
/* Read interrupt status */
|
||||
irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
|
||||
irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
|
||||
|
||||
/* Read enable mask */
|
||||
enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
|
||||
enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
|
||||
|
||||
/* and clear the interrupt */
|
||||
if (irq_status)
|
||||
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
|
||||
DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
|
||||
irq_status);
|
||||
|
||||
/* Finally update IRQ status based on enable mask */
|
||||
|
@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
|
|||
assert_spin_locked(&intr->irq_lock);
|
||||
|
||||
reg_idx = DPU_IRQ_REG(irq_idx);
|
||||
reg = &dpu_intr_set[reg_idx];
|
||||
reg = &intr->intr_set[reg_idx];
|
||||
|
||||
/* Is this interrupt register supported on the platform */
|
||||
if (WARN_ON(!reg->en_off))
|
||||
return -EINVAL;
|
||||
|
||||
cache_irq_mask = intr->cache_irq_mask[reg_idx];
|
||||
if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
|
||||
|
@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
|
|||
assert_spin_locked(&intr->irq_lock);
|
||||
|
||||
reg_idx = DPU_IRQ_REG(irq_idx);
|
||||
reg = &dpu_intr_set[reg_idx];
|
||||
reg = &intr->intr_set[reg_idx];
|
||||
|
||||
cache_irq_mask = intr->cache_irq_mask[reg_idx];
|
||||
if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
|
||||
|
@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
|
|||
if (!intr)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
|
||||
for (i = 0; i < MDP_INTR_MAX; i++) {
|
||||
if (test_bit(i, &intr->irq_mask))
|
||||
DPU_REG_WRITE(&intr->hw,
|
||||
dpu_intr_set[i].clr_off, 0xffffffff);
|
||||
intr->intr_set[i].clr_off, 0xffffffff);
|
||||
}
|
||||
|
||||
/* ensure register writes go through */
|
||||
|
@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
|
|||
if (!intr)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
|
||||
for (i = 0; i < MDP_INTR_MAX; i++) {
|
||||
if (test_bit(i, &intr->irq_mask))
|
||||
DPU_REG_WRITE(&intr->hw,
|
||||
dpu_intr_set[i].en_off, 0x00000000);
|
||||
intr->intr_set[i].en_off, 0x00000000);
|
||||
}
|
||||
|
||||
/* ensure register writes go through */
|
||||
|
@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
|
|||
|
||||
reg_idx = DPU_IRQ_REG(irq_idx);
|
||||
intr_status = DPU_REG_READ(&intr->hw,
|
||||
dpu_intr_set[reg_idx].status_off) &
|
||||
intr->intr_set[reg_idx].status_off) &
|
||||
DPU_IRQ_MASK(irq_idx);
|
||||
if (intr_status)
|
||||
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
|
||||
DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
|
||||
intr_status);
|
||||
|
||||
/* ensure register writes go through */
|
||||
|
@ -435,17 +458,12 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
|
|||
return intr_status;
|
||||
}
|
||||
|
||||
static void __intr_offset(const struct dpu_mdss_cfg *m,
|
||||
void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
|
||||
{
|
||||
hw->blk_addr = addr + m->mdp[0].base;
|
||||
}
|
||||
|
||||
struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
|
||||
const struct dpu_mdss_cfg *m)
|
||||
{
|
||||
struct dpu_hw_intr *intr;
|
||||
int nirq = MDP_INTR_MAX * 32;
|
||||
unsigned int i;
|
||||
|
||||
if (!addr || !m)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
@ -454,11 +472,29 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
|
|||
if (!intr)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
__intr_offset(m, addr, &intr->hw);
|
||||
if (m->mdss_ver->core_major_ver >= 7)
|
||||
intr->intr_set = dpu_intr_set_7xxx;
|
||||
else
|
||||
intr->intr_set = dpu_intr_set_legacy;
|
||||
|
||||
intr->hw.blk_addr = addr + m->mdp[0].base;
|
||||
|
||||
intr->total_irqs = nirq;
|
||||
|
||||
intr->irq_mask = m->mdss_irqs;
|
||||
intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
|
||||
BIT(MDP_SSPP_TOP0_INTR2) |
|
||||
BIT(MDP_SSPP_TOP0_HIST_INTR);
|
||||
for (i = 0; i < m->intf_count; i++) {
|
||||
const struct dpu_intf_cfg *intf = &m->intf[i];
|
||||
|
||||
if (intf->type == INTF_NONE)
|
||||
continue;
|
||||
|
||||
intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
|
||||
|
||||
if (intf->intr_tear_rd_ptr != -1)
|
||||
intr->irq_mask |= BIT(DPU_IRQ_REG(intf->intr_tear_rd_ptr));
|
||||
}
|
||||
|
||||
spin_lock_init(&intr->irq_lock);
|
||||
|
||||
|
|
|
@ -17,30 +17,25 @@ enum dpu_hw_intr_reg {
|
|||
MDP_SSPP_TOP0_INTR,
|
||||
MDP_SSPP_TOP0_INTR2,
|
||||
MDP_SSPP_TOP0_HIST_INTR,
|
||||
/* All MDP_INTFn_INTR should come sequentially */
|
||||
MDP_INTF0_INTR,
|
||||
MDP_INTF1_INTR,
|
||||
MDP_INTF2_INTR,
|
||||
MDP_INTF3_INTR,
|
||||
MDP_INTF4_INTR,
|
||||
MDP_INTF5_INTR,
|
||||
MDP_INTF6_INTR,
|
||||
MDP_INTF7_INTR,
|
||||
MDP_INTF8_INTR,
|
||||
MDP_INTF1_TEAR_INTR,
|
||||
MDP_INTF2_TEAR_INTR,
|
||||
MDP_AD4_0_INTR,
|
||||
MDP_AD4_1_INTR,
|
||||
MDP_INTF0_7xxx_INTR,
|
||||
MDP_INTF1_7xxx_INTR,
|
||||
MDP_INTF1_7xxx_TEAR_INTR,
|
||||
MDP_INTF2_7xxx_INTR,
|
||||
MDP_INTF2_7xxx_TEAR_INTR,
|
||||
MDP_INTF3_7xxx_INTR,
|
||||
MDP_INTF4_7xxx_INTR,
|
||||
MDP_INTF5_7xxx_INTR,
|
||||
MDP_INTF6_7xxx_INTR,
|
||||
MDP_INTF7_7xxx_INTR,
|
||||
MDP_INTF8_7xxx_INTR,
|
||||
MDP_INTR_MAX,
|
||||
};
|
||||
|
||||
#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0))
|
||||
|
||||
#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
|
||||
|
||||
/**
|
||||
|
@ -60,6 +55,7 @@ struct dpu_hw_intr {
|
|||
u32 total_irqs;
|
||||
spinlock_t irq_lock;
|
||||
unsigned long irq_mask;
|
||||
const struct dpu_intr_reg *intr_set;
|
||||
|
||||
struct {
|
||||
void (*cb)(void *arg, int irq_idx);
|
||||
|
|
|
@ -95,7 +95,7 @@
|
|||
|
||||
|
||||
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
|
||||
const struct intf_timing_params *p,
|
||||
const struct dpu_hw_intf_timing_params *p,
|
||||
const struct dpu_format *fmt)
|
||||
{
|
||||
struct dpu_hw_blk_reg_map *c = &ctx->hw;
|
||||
|
@ -244,7 +244,7 @@ static void dpu_hw_intf_enable_timing_engine(
|
|||
|
||||
static void dpu_hw_intf_setup_prg_fetch(
|
||||
struct dpu_hw_intf *intf,
|
||||
const struct intf_prog_fetch *fetch)
|
||||
const struct dpu_hw_intf_prog_fetch *fetch)
|
||||
{
|
||||
struct dpu_hw_blk_reg_map *c = &intf->hw;
|
||||
int fetch_enable;
|
||||
|
@ -286,7 +286,7 @@ static void dpu_hw_intf_bind_pingpong_blk(
|
|||
|
||||
static void dpu_hw_intf_get_status(
|
||||
struct dpu_hw_intf *intf,
|
||||
struct intf_status *s)
|
||||
struct dpu_hw_intf_status *s)
|
||||
{
|
||||
struct dpu_hw_blk_reg_map *c = &intf->hw;
|
||||
unsigned long cap = intf->cap->features;
|
||||
|
@ -513,17 +513,19 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
|
|||
|
||||
}
|
||||
|
||||
static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
|
||||
static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
|
||||
struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg)
|
||||
{
|
||||
u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
|
||||
|
||||
intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
|
||||
if (cmd_mode_cfg->data_compress)
|
||||
intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
|
||||
|
||||
DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
|
||||
}
|
||||
|
||||
static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
|
||||
unsigned long cap)
|
||||
unsigned long cap, const struct dpu_mdss_version *mdss_rev)
|
||||
{
|
||||
ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
|
||||
ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
|
||||
|
@ -543,12 +545,12 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
|
|||
ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
|
||||
}
|
||||
|
||||
if (cap & BIT(DPU_INTF_DATA_COMPRESS))
|
||||
ops->enable_compression = dpu_hw_intf_enable_compression;
|
||||
if (mdss_rev->core_major_ver >= 7)
|
||||
ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
|
||||
}
|
||||
|
||||
struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
|
||||
void __iomem *addr)
|
||||
void __iomem *addr, const struct dpu_mdss_version *mdss_rev)
|
||||
{
|
||||
struct dpu_hw_intf *c;
|
||||
|
||||
|
@ -569,7 +571,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
|
|||
*/
|
||||
c->idx = cfg->id;
|
||||
c->cap = cfg;
|
||||
_setup_intf_ops(&c->ops, c->cap->features);
|
||||
_setup_intf_ops(&c->ops, c->cap->features, mdss_rev);
|
||||
|
||||
return c;
|
||||
}
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
struct dpu_hw_intf;
|
||||
|
||||
/* intf timing settings */
|
||||
struct intf_timing_params {
|
||||
struct dpu_hw_intf_timing_params {
|
||||
u32 width; /* active width */
|
||||
u32 height; /* active height */
|
||||
u32 xres; /* Display panel width */
|
||||
|
@ -35,19 +35,23 @@ struct intf_timing_params {
|
|||
bool wide_bus_en;
|
||||
};
|
||||
|
||||
struct intf_prog_fetch {
|
||||
struct dpu_hw_intf_prog_fetch {
|
||||
u8 enable;
|
||||
/* vsync counter for the front porch pixel line */
|
||||
u32 fetch_start;
|
||||
};
|
||||
|
||||
struct intf_status {
|
||||
struct dpu_hw_intf_status {
|
||||
u8 is_en; /* interface timing engine is enabled or not */
|
||||
u8 is_prog_fetch_en; /* interface prog fetch counter is enabled or not */
|
||||
u32 frame_count; /* frame count since timing engine enabled */
|
||||
u32 line_count; /* current line count including blanking */
|
||||
};
|
||||
|
||||
struct dpu_hw_intf_cmd_mode_cfg {
|
||||
u8 data_compress; /* enable data compress between dpu and dsi */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
|
||||
* Assumption is these functions will be called after clocks are enabled
|
||||
|
@ -70,21 +74,21 @@ struct intf_status {
|
|||
* @get_autorefresh: Retrieve autorefresh config from hardware
|
||||
* Return: 0 on success, -ETIMEDOUT on timeout
|
||||
* @vsync_sel: Select vsync signal for tear-effect configuration
|
||||
* @enable_compression: Enable data compression
|
||||
* @program_intf_cmd_cfg: Program the DPU to interface datapath for command mode
|
||||
*/
|
||||
struct dpu_hw_intf_ops {
|
||||
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
|
||||
const struct intf_timing_params *p,
|
||||
const struct dpu_hw_intf_timing_params *p,
|
||||
const struct dpu_format *fmt);
|
||||
|
||||
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
|
||||
const struct intf_prog_fetch *fetch);
|
||||
const struct dpu_hw_intf_prog_fetch *fetch);
|
||||
|
||||
void (*enable_timing)(struct dpu_hw_intf *intf,
|
||||
u8 enable);
|
||||
|
||||
void (*get_status)(struct dpu_hw_intf *intf,
|
||||
struct intf_status *status);
|
||||
struct dpu_hw_intf_status *status);
|
||||
|
||||
u32 (*get_line_count)(struct dpu_hw_intf *intf);
|
||||
|
||||
|
@ -108,7 +112,8 @@ struct dpu_hw_intf_ops {
|
|||
*/
|
||||
void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
|
||||
|
||||
void (*enable_compression)(struct dpu_hw_intf *intf);
|
||||
void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,
|
||||
struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg);
|
||||
};
|
||||
|
||||
struct dpu_hw_intf {
|
||||
|
@ -127,9 +132,10 @@ struct dpu_hw_intf {
|
|||
* interface catalog entry.
|
||||
* @cfg: interface catalog entry for which driver object is required
|
||||
* @addr: mapped register io address of MDP
|
||||
* @mdss_rev: dpu core's major and minor versions
|
||||
*/
|
||||
struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
|
||||
void __iomem *addr);
|
||||
void __iomem *addr, const struct dpu_mdss_version *mdss_rev);
|
||||
|
||||
/**
|
||||
* dpu_hw_intf_destroy(): Destroys INTF driver context
|
||||
|
|
|
@ -101,11 +101,6 @@ enum dpu_hw_blk_type {
|
|||
DPU_HW_BLK_MAX,
|
||||
};
|
||||
|
||||
enum dpu_mdp {
|
||||
MDP_TOP = 0x1,
|
||||
MDP_MAX,
|
||||
};
|
||||
|
||||
enum dpu_sspp {
|
||||
SSPP_NONE,
|
||||
SSPP_VIG0,
|
||||
|
|
|
@ -8,6 +8,8 @@
|
|||
#include "dpu_hw_sspp.h"
|
||||
#include "dpu_kms.h"
|
||||
|
||||
#include "msm_mdss.h"
|
||||
|
||||
#include <drm/drm_file.h>
|
||||
|
||||
#define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087
|
||||
|
@ -270,26 +272,26 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
|
|||
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
|
||||
DPU_FETCH_CONFIG_RESET_VALUE |
|
||||
ctx->ubwc->highest_bank_bit << 18);
|
||||
switch (ctx->ubwc->ubwc_version) {
|
||||
case DPU_HW_UBWC_VER_10:
|
||||
switch (ctx->ubwc->ubwc_enc_version) {
|
||||
case UBWC_1_0:
|
||||
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
|
||||
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
|
||||
fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
|
||||
BIT(8) |
|
||||
(ctx->ubwc->highest_bank_bit << 4));
|
||||
break;
|
||||
case DPU_HW_UBWC_VER_20:
|
||||
case UBWC_2_0:
|
||||
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
|
||||
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
|
||||
fast_clear | (ctx->ubwc->ubwc_swizzle) |
|
||||
(ctx->ubwc->highest_bank_bit << 4));
|
||||
break;
|
||||
case DPU_HW_UBWC_VER_30:
|
||||
case UBWC_3_0:
|
||||
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
|
||||
BIT(30) | (ctx->ubwc->ubwc_swizzle) |
|
||||
(ctx->ubwc->highest_bank_bit << 4));
|
||||
break;
|
||||
case DPU_HW_UBWC_VER_40:
|
||||
case UBWC_4_0:
|
||||
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
|
||||
DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
|
||||
break;
|
||||
|
@ -670,11 +672,11 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
|
|||
#endif
|
||||
|
||||
struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
|
||||
void __iomem *addr, const struct dpu_ubwc_cfg *ubwc)
|
||||
void __iomem *addr, const struct msm_mdss_data *mdss_data)
|
||||
{
|
||||
struct dpu_hw_sspp *hw_pipe;
|
||||
|
||||
if (!addr || !ubwc)
|
||||
if (!addr)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
|
||||
|
@ -685,7 +687,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
|
|||
hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP;
|
||||
|
||||
/* Assign ops */
|
||||
hw_pipe->ubwc = ubwc;
|
||||
hw_pipe->ubwc = mdss_data;
|
||||
hw_pipe->idx = cfg->id;
|
||||
hw_pipe->cap = cfg;
|
||||
_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
|
||||
|
|
|
@ -317,7 +317,7 @@ struct dpu_hw_sspp_ops {
|
|||
struct dpu_hw_sspp {
|
||||
struct dpu_hw_blk base;
|
||||
struct dpu_hw_blk_reg_map hw;
|
||||
const struct dpu_ubwc_cfg *ubwc;
|
||||
const struct msm_mdss_data *ubwc;
|
||||
|
||||
/* Pipe */
|
||||
enum dpu_sspp idx;
|
||||
|
@ -333,10 +333,10 @@ struct dpu_kms;
|
|||
* Should be called once before accessing every pipe.
|
||||
* @cfg: Pipe catalog entry for which driver object is required
|
||||
* @addr: Mapped register io address of MDP
|
||||
* @ubwc: UBWC configuration data
|
||||
* @mdss_data: UBWC / MDSS configuration data
|
||||
*/
|
||||
struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
|
||||
void __iomem *addr, const struct dpu_ubwc_cfg *ubwc);
|
||||
void __iomem *addr, const struct msm_mdss_data *mdss_data);
|
||||
|
||||
/**
|
||||
* dpu_hw_sspp_destroy(): Destroys SSPP driver context
|
||||
|
|
|
@ -268,51 +268,25 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
|
|||
ops->intf_audio_select = dpu_hw_intf_audio_select;
|
||||
}
|
||||
|
||||
static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
|
||||
const struct dpu_mdss_cfg *m,
|
||||
void __iomem *addr,
|
||||
struct dpu_hw_blk_reg_map *b)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!m || !addr || !b)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
for (i = 0; i < m->mdp_count; i++) {
|
||||
if (mdp == m->mdp[i].id) {
|
||||
b->blk_addr = addr + m->mdp[i].base;
|
||||
b->log_mask = DPU_DBG_MASK_TOP;
|
||||
return &m->mdp[i];
|
||||
}
|
||||
}
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
|
||||
struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
|
||||
void __iomem *addr,
|
||||
const struct dpu_mdss_cfg *m)
|
||||
{
|
||||
struct dpu_hw_mdp *mdp;
|
||||
const struct dpu_mdp_cfg *cfg;
|
||||
|
||||
if (!addr || !m)
|
||||
if (!addr)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
|
||||
if (!mdp)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
cfg = _top_offset(idx, m, addr, &mdp->hw);
|
||||
if (IS_ERR_OR_NULL(cfg)) {
|
||||
kfree(mdp);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
mdp->hw.blk_addr = addr + cfg->base;
|
||||
mdp->hw.log_mask = DPU_DBG_MASK_TOP;
|
||||
|
||||
/*
|
||||
* Assign ops
|
||||
*/
|
||||
mdp->idx = idx;
|
||||
mdp->caps = cfg;
|
||||
_setup_mdp_ops(&mdp->ops, mdp->caps->features);
|
||||
|
||||
|
|
|
@ -137,7 +137,6 @@ struct dpu_hw_mdp {
|
|||
struct dpu_hw_blk_reg_map hw;
|
||||
|
||||
/* top */
|
||||
enum dpu_mdp idx;
|
||||
const struct dpu_mdp_cfg *caps;
|
||||
|
||||
/* ops */
|
||||
|
@ -145,12 +144,12 @@ struct dpu_hw_mdp {
|
|||
};
|
||||
|
||||
/**
|
||||
* dpu_hw_mdptop_init - initializes the top driver for the passed idx
|
||||
* @idx: Interface index for which driver object is required
|
||||
* dpu_hw_mdptop_init - initializes the top driver for the passed config
|
||||
* @cfg: MDP TOP configuration from catalog
|
||||
* @addr: Mapped register io address of MDP
|
||||
* @m: Pointer to mdss catalog data
|
||||
*/
|
||||
struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
|
||||
struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
|
||||
void __iomem *addr,
|
||||
const struct dpu_mdss_cfg *m);
|
||||
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#include "msm_drv.h"
|
||||
#include "msm_mmu.h"
|
||||
#include "msm_mdss.h"
|
||||
#include "msm_gem.h"
|
||||
#include "disp/msm_disp_snapshot.h"
|
||||
|
||||
|
@ -544,8 +545,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
|
|||
|
||||
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
|
||||
|
||||
info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
|
||||
|
||||
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info);
|
||||
if (IS_ERR(encoder)) {
|
||||
DPU_ERROR("encoder init failed for dsi display\n");
|
||||
|
@ -794,7 +793,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
|
|||
ret = PTR_ERR(crtc);
|
||||
return ret;
|
||||
}
|
||||
priv->crtcs[priv->num_crtcs++] = crtc;
|
||||
priv->num_crtcs++;
|
||||
}
|
||||
|
||||
/* All CRTCs are compatible with all encoders */
|
||||
|
@ -890,6 +889,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
|
|||
int i;
|
||||
struct dpu_kms *dpu_kms;
|
||||
const struct dpu_mdss_cfg *cat;
|
||||
void __iomem *base;
|
||||
|
||||
dpu_kms = to_dpu_kms(kms);
|
||||
|
||||
|
@ -900,37 +900,67 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
|
|||
/* dump CTL sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->ctl_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
|
||||
dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
|
||||
dpu_kms->mmio + cat->ctl[i].base, cat->ctl[i].name);
|
||||
|
||||
/* dump DSPP sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->dspp_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
|
||||
dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
|
||||
for (i = 0; i < cat->dspp_count; i++) {
|
||||
base = dpu_kms->mmio + cat->dspp[i].base;
|
||||
msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, cat->dspp[i].name);
|
||||
|
||||
if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len,
|
||||
base + cat->dspp[i].sblk->pcc.base, "%s_%s",
|
||||
cat->dspp[i].name,
|
||||
cat->dspp[i].sblk->pcc.name);
|
||||
}
|
||||
|
||||
/* dump INTF sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->intf_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
|
||||
dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
|
||||
dpu_kms->mmio + cat->intf[i].base, cat->intf[i].name);
|
||||
|
||||
/* dump PP sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->pingpong_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
|
||||
dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
|
||||
for (i = 0; i < cat->pingpong_count; i++) {
|
||||
base = dpu_kms->mmio + cat->pingpong[i].base;
|
||||
msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base,
|
||||
cat->pingpong[i].name);
|
||||
|
||||
/* TE2 sub-block has length of 0, so will not print it */
|
||||
|
||||
if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len,
|
||||
base + cat->pingpong[i].sblk->dither.base,
|
||||
"%s_%s", cat->pingpong[i].name,
|
||||
cat->pingpong[i].sblk->dither.name);
|
||||
}
|
||||
|
||||
/* dump SSPP sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->sspp_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
|
||||
dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
|
||||
for (i = 0; i < cat->sspp_count; i++) {
|
||||
base = dpu_kms->mmio + cat->sspp[i].base;
|
||||
msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, cat->sspp[i].name);
|
||||
|
||||
if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len,
|
||||
base + cat->sspp[i].sblk->scaler_blk.base,
|
||||
"%s_%s", cat->sspp[i].name,
|
||||
cat->sspp[i].sblk->scaler_blk.name);
|
||||
|
||||
if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len,
|
||||
base + cat->sspp[i].sblk->csc_blk.base,
|
||||
"%s_%s", cat->sspp[i].name,
|
||||
cat->sspp[i].sblk->csc_blk.name);
|
||||
}
|
||||
|
||||
/* dump LM sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->mixer_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
|
||||
dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i);
|
||||
dpu_kms->mmio + cat->mixer[i].base, cat->mixer[i].name);
|
||||
|
||||
/* dump WB sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->wb_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
|
||||
dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
|
||||
dpu_kms->mmio + cat->wb[i].base, cat->wb[i].name);
|
||||
|
||||
if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
|
||||
msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
|
||||
|
@ -943,9 +973,20 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
|
|||
}
|
||||
|
||||
/* dump DSC sub-blocks HW regs info */
|
||||
for (i = 0; i < cat->dsc_count; i++)
|
||||
msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len,
|
||||
dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i);
|
||||
for (i = 0; i < cat->dsc_count; i++) {
|
||||
base = dpu_kms->mmio + cat->dsc[i].base;
|
||||
msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, cat->dsc[i].name);
|
||||
|
||||
if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
|
||||
struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
|
||||
struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
|
||||
|
||||
msm_disp_snapshot_add_block(disp_state, enc.len, base + enc.base, "%s_%s",
|
||||
cat->dsc[i].name, enc.name);
|
||||
msm_disp_snapshot_add_block(disp_state, ctl.len, base + ctl.base, "%s_%s",
|
||||
cat->dsc[i].name, ctl.name);
|
||||
}
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(&dpu_kms->pdev->dev);
|
||||
}
|
||||
|
@ -1011,11 +1052,14 @@ unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
|
|||
return clk_get_rate(clk);
|
||||
}
|
||||
|
||||
#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
|
||||
|
||||
static int dpu_kms_hw_init(struct msm_kms *kms)
|
||||
{
|
||||
struct dpu_kms *dpu_kms;
|
||||
struct drm_device *dev;
|
||||
int i, rc = -EINVAL;
|
||||
unsigned long max_core_clk_rate;
|
||||
u32 core_rev;
|
||||
|
||||
if (!kms) {
|
||||
|
@ -1084,7 +1128,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
|
|||
goto power_error;
|
||||
}
|
||||
|
||||
rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
|
||||
dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);
|
||||
if (IS_ERR(dpu_kms->mdss)) {
|
||||
rc = PTR_ERR(dpu_kms->mdss);
|
||||
DPU_ERROR("failed to get MDSS data: %d\n", rc);
|
||||
goto power_error;
|
||||
}
|
||||
|
||||
if (!dpu_kms->mdss) {
|
||||
rc = -EINVAL;
|
||||
DPU_ERROR("NULL MDSS data\n");
|
||||
goto power_error;
|
||||
}
|
||||
|
||||
rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio);
|
||||
if (rc) {
|
||||
DPU_ERROR("rm init failed: %d\n", rc);
|
||||
goto power_error;
|
||||
|
@ -1092,7 +1149,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
|
|||
|
||||
dpu_kms->rm_init = true;
|
||||
|
||||
dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
|
||||
dpu_kms->hw_mdp = dpu_hw_mdptop_init(dpu_kms->catalog->mdp,
|
||||
dpu_kms->mmio,
|
||||
dpu_kms->catalog);
|
||||
if (IS_ERR(dpu_kms->hw_mdp)) {
|
||||
rc = PTR_ERR(dpu_kms->hw_mdp);
|
||||
|
@ -1115,8 +1173,14 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
|
|||
dpu_kms->hw_vbif[vbif->id] = hw;
|
||||
}
|
||||
|
||||
rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
|
||||
msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core"));
|
||||
/* TODO: use the same max_freq as in dpu_kms_hw_init */
|
||||
max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core");
|
||||
if (!max_core_clk_rate) {
|
||||
DPU_DEBUG("max core clk rate not determined, using default\n");
|
||||
max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
|
||||
}
|
||||
|
||||
rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate);
|
||||
if (rc) {
|
||||
DPU_ERROR("failed to init perf %d\n", rc);
|
||||
goto perf_err;
|
||||
|
@ -1162,7 +1226,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
|
|||
return 0;
|
||||
|
||||
drm_obj_init_err:
|
||||
dpu_core_perf_destroy(&dpu_kms->perf);
|
||||
hw_intr_init_err:
|
||||
perf_err:
|
||||
power_error:
|
||||
|
@ -1305,6 +1368,7 @@ static const struct of_device_id dpu_dt_match[] = {
|
|||
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
|
||||
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
|
||||
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
|
||||
{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
|
||||
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
|
||||
{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
|
||||
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
|
||||
|
|
|
@ -67,6 +67,7 @@ struct dpu_kms {
|
|||
struct msm_kms base;
|
||||
struct drm_device *dev;
|
||||
const struct dpu_mdss_cfg *catalog;
|
||||
const struct msm_mdss_data *mdss;
|
||||
|
||||
/* io/register spaces: */
|
||||
void __iomem *mmio, *vbif[VBIF_MAX];
|
||||
|
|
|
@ -101,6 +101,7 @@ int dpu_rm_destroy(struct dpu_rm *rm)
|
|||
|
||||
int dpu_rm_init(struct dpu_rm *rm,
|
||||
const struct dpu_mdss_cfg *cat,
|
||||
const struct msm_mdss_data *mdss_data,
|
||||
void __iomem *mmio)
|
||||
{
|
||||
int rc, i;
|
||||
|
@ -161,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm,
|
|||
struct dpu_hw_intf *hw;
|
||||
const struct dpu_intf_cfg *intf = &cat->intf[i];
|
||||
|
||||
hw = dpu_hw_intf_init(intf, mmio);
|
||||
hw = dpu_hw_intf_init(intf, mmio, cat->mdss_ver);
|
||||
if (IS_ERR(hw)) {
|
||||
rc = PTR_ERR(hw);
|
||||
DPU_ERROR("failed intf object creation: err %d\n", rc);
|
||||
|
@ -230,7 +231,7 @@ int dpu_rm_init(struct dpu_rm *rm,
|
|||
struct dpu_hw_sspp *hw;
|
||||
const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
|
||||
|
||||
hw = dpu_hw_sspp_init(sspp, mmio, cat->ubwc);
|
||||
hw = dpu_hw_sspp_init(sspp, mmio, mdss_data);
|
||||
if (IS_ERR(hw)) {
|
||||
rc = PTR_ERR(hw);
|
||||
DPU_ERROR("failed sspp object creation: err %d\n", rc);
|
||||
|
@ -253,28 +254,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
|
|||
}
|
||||
|
||||
/**
|
||||
* _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary
|
||||
* _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary
|
||||
* @rm: dpu resource manager handle
|
||||
* @primary_idx: index of primary mixer in rm->mixer_blks[]
|
||||
* @peer_idx: index of other mixer in rm->mixer_blks[]
|
||||
* Return: true if rm->mixer_blks[peer_idx] is a peer of
|
||||
* rm->mixer_blks[primary_idx]
|
||||
*/
|
||||
static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx,
|
||||
int peer_idx)
|
||||
static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
|
||||
{
|
||||
const struct dpu_lm_cfg *prim_lm_cfg;
|
||||
const struct dpu_lm_cfg *peer_cfg;
|
||||
|
||||
prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap;
|
||||
peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;
|
||||
|
||||
if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
|
||||
DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id,
|
||||
peer_cfg->id);
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX)
|
||||
return prim_lm_cfg->lm_pair - LM_0;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -351,7 +343,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
|
|||
int lm_idx[MAX_BLOCKS];
|
||||
int pp_idx[MAX_BLOCKS];
|
||||
int dspp_idx[MAX_BLOCKS] = {0};
|
||||
int i, j, lm_count = 0;
|
||||
int i, lm_count = 0;
|
||||
|
||||
if (!reqs->topology.num_lm) {
|
||||
DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
|
||||
|
@ -376,16 +368,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
|
|||
++lm_count;
|
||||
|
||||
/* Valid primary mixer found, find matching peers */
|
||||
for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) &&
|
||||
lm_count < reqs->topology.num_lm; j++) {
|
||||
if (!rm->mixer_blks[j])
|
||||
if (lm_count < reqs->topology.num_lm) {
|
||||
int j = _dpu_rm_get_lm_peer(rm, i);
|
||||
|
||||
/* ignore the peer if there is an error or if the peer was already processed */
|
||||
if (j < 0 || j < i)
|
||||
continue;
|
||||
|
||||
if (!_dpu_rm_check_lm_peer(rm, i, j)) {
|
||||
DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j,
|
||||
LM_0 + i);
|
||||
if (!rm->mixer_blks[j])
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!_dpu_rm_check_lm_and_get_connected_blks(rm,
|
||||
global_state, enc_id, j,
|
||||
|
|
|
@ -40,11 +40,13 @@ struct dpu_rm {
|
|||
* for all HW blocks.
|
||||
* @rm: DPU Resource Manager handle
|
||||
* @cat: Pointer to hardware catalog
|
||||
* @mdss_data: Pointer to MDSS / UBWC configuration
|
||||
* @mmio: mapped register io address of MDP
|
||||
* @Return: 0 on Success otherwise -ERROR
|
||||
*/
|
||||
int dpu_rm_init(struct dpu_rm *rm,
|
||||
const struct dpu_mdss_cfg *cat,
|
||||
const struct msm_mdss_data *mdss_data,
|
||||
void __iomem *mmio);
|
||||
|
||||
/**
|
||||
|
|
|
@ -453,29 +453,6 @@ TRACE_EVENT(dpu_enc_trigger_flush,
|
|||
__entry->extra_flush_bits, __entry->pending_flush_ret)
|
||||
);
|
||||
|
||||
DECLARE_EVENT_CLASS(dpu_enc_ktime_template,
|
||||
TP_PROTO(uint32_t drm_id, ktime_t time),
|
||||
TP_ARGS(drm_id, time),
|
||||
TP_STRUCT__entry(
|
||||
__field( uint32_t, drm_id )
|
||||
__field( ktime_t, time )
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->drm_id = drm_id;
|
||||
__entry->time = time;
|
||||
),
|
||||
TP_printk("id=%u, time=%lld", __entry->drm_id,
|
||||
ktime_to_ms(__entry->time))
|
||||
);
|
||||
DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work,
|
||||
TP_PROTO(uint32_t drm_id, ktime_t time),
|
||||
TP_ARGS(drm_id, time)
|
||||
);
|
||||
DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff,
|
||||
TP_PROTO(uint32_t drm_id, ktime_t time),
|
||||
TP_ARGS(drm_id, time)
|
||||
);
|
||||
|
||||
DECLARE_EVENT_CLASS(dpu_id_event_template,
|
||||
TP_PROTO(uint32_t drm_id, u32 event),
|
||||
TP_ARGS(drm_id, event),
|
||||
|
|
|
@ -332,7 +332,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
priv->crtcs[priv->num_crtcs++] = crtc;
|
||||
priv->num_crtcs++;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -417,7 +417,6 @@ static int mdp4_kms_init(struct drm_device *dev)
|
|||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
ret = irq;
|
||||
DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
|
|
@ -497,7 +497,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
|
|||
DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
|
||||
goto fail;
|
||||
}
|
||||
priv->crtcs[priv->num_crtcs++] = crtc;
|
||||
priv->num_crtcs++;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -130,8 +130,7 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane,
|
|||
{
|
||||
struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
|
||||
|
||||
if (state->fb)
|
||||
drm_framebuffer_put(state->fb);
|
||||
__drm_atomic_helper_plane_destroy_state(state);
|
||||
|
||||
kfree(pstate);
|
||||
}
|
||||
|
|
|
@ -192,5 +192,5 @@ void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
|
|||
new_blk->base_addr = base_addr;
|
||||
|
||||
msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr);
|
||||
list_add(&new_blk->node, &disp_state->blocks);
|
||||
list_add_tail(&new_blk->node, &disp_state->blocks);
|
||||
}
|
||||
|
|
|
@ -160,6 +160,7 @@ static const char * const dsi_v2_4_clk_names[] = {
|
|||
|
||||
static const struct regulator_bulk_data dsi_v2_4_regulators[] = {
|
||||
{ .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */
|
||||
{ .supply = "refgen" },
|
||||
};
|
||||
|
||||
static const struct msm_dsi_config sdm845_dsi_cfg = {
|
||||
|
@ -191,6 +192,7 @@ static const struct msm_dsi_config sm8550_dsi_cfg = {
|
|||
|
||||
static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
|
||||
{ .supply = "vdda", .init_load_uA = 8350 }, /* 1.2 V */
|
||||
{ .supply = "refgen" },
|
||||
};
|
||||
|
||||
static const struct msm_dsi_config sc7280_dsi_cfg = {
|
||||
|
|
|
@ -752,6 +752,13 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
|
|||
/* Always insert DCS command */
|
||||
data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
|
||||
dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
|
||||
|
||||
if (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
|
||||
msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) {
|
||||
data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2);
|
||||
data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
|
||||
dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data);
|
||||
}
|
||||
}
|
||||
|
||||
dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
|
||||
|
|
|
@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
|
|||
.data = &dsi_phy_14nm_660_cfgs },
|
||||
{ .compatible = "qcom,dsi-phy-14nm-8953",
|
||||
.data = &dsi_phy_14nm_8953_cfgs },
|
||||
{ .compatible = "qcom,sm6125-dsi-phy-14nm",
|
||||
.data = &dsi_phy_14nm_2290_cfgs },
|
||||
#endif
|
||||
#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
|
||||
{ .compatible = "qcom,dsi-phy-10nm",
|
||||
|
|
|
@ -155,7 +155,7 @@ static void msm_irq_uninstall(struct drm_device *dev)
|
|||
|
||||
struct msm_vblank_work {
|
||||
struct work_struct work;
|
||||
int crtc_id;
|
||||
struct drm_crtc *crtc;
|
||||
bool enable;
|
||||
struct msm_drm_private *priv;
|
||||
};
|
||||
|
@ -168,15 +168,15 @@ static void vblank_ctrl_worker(struct work_struct *work)
|
|||
struct msm_kms *kms = priv->kms;
|
||||
|
||||
if (vbl_work->enable)
|
||||
kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
|
||||
kms->funcs->enable_vblank(kms, vbl_work->crtc);
|
||||
else
|
||||
kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
|
||||
kms->funcs->disable_vblank(kms, vbl_work->crtc);
|
||||
|
||||
kfree(vbl_work);
|
||||
}
|
||||
|
||||
static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
|
||||
int crtc_id, bool enable)
|
||||
struct drm_crtc *crtc, bool enable)
|
||||
{
|
||||
struct msm_vblank_work *vbl_work;
|
||||
|
||||
|
@ -186,7 +186,7 @@ static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
|
|||
|
||||
INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
|
||||
|
||||
vbl_work->crtc_id = crtc_id;
|
||||
vbl_work->crtc = crtc;
|
||||
vbl_work->enable = enable;
|
||||
vbl_work->priv = priv;
|
||||
|
||||
|
@ -407,7 +407,8 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
|
|||
struct msm_drm_private *priv = dev_get_drvdata(dev);
|
||||
struct drm_device *ddev;
|
||||
struct msm_kms *kms;
|
||||
int ret, i;
|
||||
struct drm_crtc *crtc;
|
||||
int ret;
|
||||
|
||||
if (drm_firmware_drivers_only())
|
||||
return -ENODEV;
|
||||
|
@ -494,20 +495,21 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
|
|||
ddev->mode_config.funcs = &mode_config_funcs;
|
||||
ddev->mode_config.helper_private = &mode_config_helper_funcs;
|
||||
|
||||
for (i = 0; i < priv->num_crtcs; i++) {
|
||||
drm_for_each_crtc(crtc, ddev) {
|
||||
struct msm_drm_thread *ev_thread;
|
||||
|
||||
/* initialize event thread */
|
||||
priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
|
||||
priv->event_thread[i].dev = ddev;
|
||||
priv->event_thread[i].worker = kthread_create_worker(0,
|
||||
"crtc_event:%d", priv->event_thread[i].crtc_id);
|
||||
if (IS_ERR(priv->event_thread[i].worker)) {
|
||||
ret = PTR_ERR(priv->event_thread[i].worker);
|
||||
ev_thread = &priv->event_thread[drm_crtc_index(crtc)];
|
||||
ev_thread->dev = ddev;
|
||||
ev_thread->worker = kthread_create_worker(0, "crtc_event:%d", crtc->base.id);
|
||||
if (IS_ERR(ev_thread->worker)) {
|
||||
ret = PTR_ERR(ev_thread->worker);
|
||||
DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
|
||||
priv->event_thread[i].worker = NULL;
|
||||
ev_thread->worker = NULL;
|
||||
goto err_msm_uninit;
|
||||
}
|
||||
|
||||
sched_set_fifo(priv->event_thread[i].worker->task);
|
||||
sched_set_fifo(ev_thread->worker->task);
|
||||
}
|
||||
|
||||
ret = drm_vblank_init(ddev, priv->num_crtcs);
|
||||
|
@ -639,25 +641,23 @@ static void msm_postclose(struct drm_device *dev, struct drm_file *file)
|
|||
int msm_crtc_enable_vblank(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
unsigned int pipe = crtc->index;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct msm_kms *kms = priv->kms;
|
||||
if (!kms)
|
||||
return -ENXIO;
|
||||
drm_dbg_vbl(dev, "crtc=%u", pipe);
|
||||
return vblank_ctrl_queue_work(priv, pipe, true);
|
||||
drm_dbg_vbl(dev, "crtc=%u", crtc->base.id);
|
||||
return vblank_ctrl_queue_work(priv, crtc, true);
|
||||
}
|
||||
|
||||
void msm_crtc_disable_vblank(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
unsigned int pipe = crtc->index;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct msm_kms *kms = priv->kms;
|
||||
if (!kms)
|
||||
return;
|
||||
drm_dbg_vbl(dev, "crtc=%u", pipe);
|
||||
vblank_ctrl_queue_work(priv, pipe, false);
|
||||
drm_dbg_vbl(dev, "crtc=%u", crtc->base.id);
|
||||
vblank_ctrl_queue_work(priv, crtc, false);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -65,6 +65,12 @@ enum msm_dp_controller {
|
|||
MSM_DP_CONTROLLER_COUNT,
|
||||
};
|
||||
|
||||
enum msm_dsi_controller {
|
||||
MSM_DSI_CONTROLLER_0,
|
||||
MSM_DSI_CONTROLLER_1,
|
||||
MSM_DSI_CONTROLLER_COUNT,
|
||||
};
|
||||
|
||||
#define MSM_GPU_MAX_RINGS 4
|
||||
#define MAX_H_TILES_PER_DISPLAY 2
|
||||
|
||||
|
@ -97,7 +103,6 @@ struct msm_display_topology {
|
|||
/* Commit/Event thread specific structure */
|
||||
struct msm_drm_thread {
|
||||
struct drm_device *dev;
|
||||
unsigned int crtc_id;
|
||||
struct kthread_worker *worker;
|
||||
};
|
||||
|
||||
|
@ -117,7 +122,7 @@ struct msm_drm_private {
|
|||
struct hdmi *hdmi;
|
||||
|
||||
/* DSI is shared by mdp4 and mdp5 */
|
||||
struct msm_dsi *dsi[2];
|
||||
struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
|
||||
|
||||
struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
|
||||
|
||||
|
@ -198,7 +203,6 @@ struct msm_drm_private {
|
|||
struct workqueue_struct *wq;
|
||||
|
||||
unsigned int num_crtcs;
|
||||
struct drm_crtc *crtcs[MAX_CRTCS];
|
||||
|
||||
struct msm_drm_thread event_thread[MAX_CRTCS];
|
||||
|
||||
|
|
|
@ -222,9 +222,7 @@ static void put_pages(struct drm_gem_object *obj)
|
|||
static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj,
|
||||
unsigned madv)
|
||||
{
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct page **p;
|
||||
|
||||
msm_gem_assert_locked(obj);
|
||||
|
||||
|
@ -234,16 +232,29 @@ static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj,
|
|||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
p = get_pages(obj);
|
||||
if (IS_ERR(p))
|
||||
return p;
|
||||
return get_pages(obj);
|
||||
}
|
||||
|
||||
/*
|
||||
* Update the pin count of the object, call under lru.lock
|
||||
*/
|
||||
void msm_gem_pin_obj_locked(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
|
||||
msm_gem_assert_locked(obj);
|
||||
|
||||
to_msm_bo(obj)->pin_count++;
|
||||
drm_gem_lru_move_tail_locked(&priv->lru.pinned, obj);
|
||||
}
|
||||
|
||||
static void pin_obj_locked(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
|
||||
mutex_lock(&priv->lru.lock);
|
||||
msm_obj->pin_count++;
|
||||
update_lru_locked(obj);
|
||||
msm_gem_pin_obj_locked(obj);
|
||||
mutex_unlock(&priv->lru.lock);
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
struct page **msm_gem_pin_pages(struct drm_gem_object *obj)
|
||||
|
@ -252,6 +263,8 @@ struct page **msm_gem_pin_pages(struct drm_gem_object *obj)
|
|||
|
||||
msm_gem_lock(obj);
|
||||
p = msm_gem_pin_pages_locked(obj, MSM_MADV_WILLNEED);
|
||||
if (!IS_ERR(p))
|
||||
pin_obj_locked(obj);
|
||||
msm_gem_unlock(obj);
|
||||
|
||||
return p;
|
||||
|
@ -463,7 +476,7 @@ int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma)
|
|||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct page **pages;
|
||||
int ret, prot = IOMMU_READ;
|
||||
int prot = IOMMU_READ;
|
||||
|
||||
if (!(msm_obj->flags & MSM_BO_GPU_READONLY))
|
||||
prot |= IOMMU_WRITE;
|
||||
|
@ -480,11 +493,7 @@ int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma)
|
|||
if (IS_ERR(pages))
|
||||
return PTR_ERR(pages);
|
||||
|
||||
ret = msm_gem_vma_map(vma, prot, msm_obj->sgt, obj->size);
|
||||
if (ret)
|
||||
msm_gem_unpin_locked(obj);
|
||||
|
||||
return ret;
|
||||
return msm_gem_vma_map(vma, prot, msm_obj->sgt, obj->size);
|
||||
}
|
||||
|
||||
void msm_gem_unpin_locked(struct drm_gem_object *obj)
|
||||
|
@ -509,14 +518,11 @@ void msm_gem_unpin_locked(struct drm_gem_object *obj)
|
|||
*/
|
||||
void msm_gem_unpin_active(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
||||
mutex_lock(&priv->lru.lock);
|
||||
msm_obj->pin_count--;
|
||||
GEM_WARN_ON(msm_obj->pin_count < 0);
|
||||
update_lru_active(obj);
|
||||
mutex_unlock(&priv->lru.lock);
|
||||
}
|
||||
|
||||
struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
|
||||
|
@ -539,8 +545,10 @@ static int get_and_pin_iova_range_locked(struct drm_gem_object *obj,
|
|||
return PTR_ERR(vma);
|
||||
|
||||
ret = msm_gem_pin_vma_locked(obj, vma);
|
||||
if (!ret)
|
||||
if (!ret) {
|
||||
*iova = vma->iova;
|
||||
pin_obj_locked(obj);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -599,9 +607,6 @@ static int clear_iova(struct drm_gem_object *obj,
|
|||
if (!vma)
|
||||
return 0;
|
||||
|
||||
if (msm_gem_vma_inuse(vma))
|
||||
return -EBUSY;
|
||||
|
||||
msm_gem_vma_purge(vma);
|
||||
msm_gem_vma_close(vma);
|
||||
del_vma(vma);
|
||||
|
@ -652,7 +657,6 @@ void msm_gem_unpin_iova(struct drm_gem_object *obj,
|
|||
msm_gem_lock(obj);
|
||||
vma = lookup_vma(obj, aspace);
|
||||
if (!GEM_WARN_ON(!vma)) {
|
||||
msm_gem_vma_unpin(vma);
|
||||
msm_gem_unpin_locked(obj);
|
||||
}
|
||||
msm_gem_unlock(obj);
|
||||
|
@ -703,6 +707,8 @@ static void *get_vaddr(struct drm_gem_object *obj, unsigned madv)
|
|||
if (IS_ERR(pages))
|
||||
return ERR_CAST(pages);
|
||||
|
||||
pin_obj_locked(obj);
|
||||
|
||||
/* increment vmap_count *before* vmap() call, so shrinker can
|
||||
* check vmap_count (is_vunmapable()) outside of msm_obj lock.
|
||||
* This guarantees that we won't try to msm_gem_vunmap() this
|
||||
|
@ -981,11 +987,10 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m,
|
|||
} else {
|
||||
name = comm = NULL;
|
||||
}
|
||||
seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s,inuse=%d]",
|
||||
seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s]",
|
||||
name, comm ? ":" : "", comm ? comm : "",
|
||||
vma->aspace, vma->iova,
|
||||
vma->mapped ? "mapped" : "unmapped",
|
||||
msm_gem_vma_inuse(vma));
|
||||
vma->mapped ? "mapped" : "unmapped");
|
||||
kfree(comm);
|
||||
}
|
||||
|
||||
|
|
|
@ -59,24 +59,16 @@ struct msm_fence_context;
|
|||
|
||||
struct msm_gem_vma {
|
||||
struct drm_mm_node node;
|
||||
spinlock_t lock;
|
||||
uint64_t iova;
|
||||
struct msm_gem_address_space *aspace;
|
||||
struct list_head list; /* node in msm_gem_object::vmas */
|
||||
bool mapped;
|
||||
int inuse;
|
||||
uint32_t fence_mask;
|
||||
uint32_t fence[MSM_GPU_MAX_RINGS];
|
||||
struct msm_fence_context *fctx[MSM_GPU_MAX_RINGS];
|
||||
};
|
||||
|
||||
struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_address_space *aspace);
|
||||
int msm_gem_vma_init(struct msm_gem_vma *vma, int size,
|
||||
u64 range_start, u64 range_end);
|
||||
bool msm_gem_vma_inuse(struct msm_gem_vma *vma);
|
||||
void msm_gem_vma_purge(struct msm_gem_vma *vma);
|
||||
void msm_gem_vma_unpin(struct msm_gem_vma *vma);
|
||||
void msm_gem_vma_unpin_fenced(struct msm_gem_vma *vma, struct msm_fence_context *fctx);
|
||||
int msm_gem_vma_map(struct msm_gem_vma *vma, int prot, struct sg_table *sgt, int size);
|
||||
void msm_gem_vma_close(struct msm_gem_vma *vma);
|
||||
|
||||
|
@ -142,6 +134,7 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
|
|||
struct msm_gem_address_space *aspace, uint64_t *iova);
|
||||
void msm_gem_unpin_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace);
|
||||
void msm_gem_pin_obj_locked(struct drm_gem_object *obj);
|
||||
struct page **msm_gem_pin_pages(struct drm_gem_object *obj);
|
||||
void msm_gem_unpin_pages(struct drm_gem_object *obj);
|
||||
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
||||
|
@ -297,15 +290,13 @@ struct msm_gem_submit {
|
|||
/* make sure these don't conflict w/ MSM_SUBMIT_BO_x */
|
||||
#define BO_VALID 0x8000 /* is current addr in cmdstream correct/valid? */
|
||||
#define BO_LOCKED 0x4000 /* obj lock is held */
|
||||
#define BO_OBJ_PINNED 0x2000 /* obj (pages) is pinned and on active list */
|
||||
#define BO_VMA_PINNED 0x1000 /* vma (virtual address) is pinned */
|
||||
#define BO_PINNED 0x2000 /* obj (pages) is pinned and on active list */
|
||||
uint32_t flags;
|
||||
union {
|
||||
struct msm_gem_object *obj;
|
||||
struct drm_gem_object *obj;
|
||||
uint32_t handle;
|
||||
};
|
||||
uint64_t iova;
|
||||
struct msm_gem_vma *vma;
|
||||
} bos[];
|
||||
};
|
||||
|
||||
|
|
|
@ -165,7 +165,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,
|
|||
|
||||
drm_gem_object_get(obj);
|
||||
|
||||
submit->bos[i].obj = to_msm_bo(obj);
|
||||
submit->bos[i].obj = obj;
|
||||
}
|
||||
|
||||
out_unlock:
|
||||
|
@ -251,7 +251,7 @@ out:
|
|||
static void submit_cleanup_bo(struct msm_gem_submit *submit, int i,
|
||||
unsigned cleanup_flags)
|
||||
{
|
||||
struct drm_gem_object *obj = &submit->bos[i].obj->base;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
unsigned flags = submit->bos[i].flags & cleanup_flags;
|
||||
|
||||
/*
|
||||
|
@ -261,10 +261,7 @@ static void submit_cleanup_bo(struct msm_gem_submit *submit, int i,
|
|||
*/
|
||||
submit->bos[i].flags &= ~cleanup_flags;
|
||||
|
||||
if (flags & BO_VMA_PINNED)
|
||||
msm_gem_vma_unpin(submit->bos[i].vma);
|
||||
|
||||
if (flags & BO_OBJ_PINNED)
|
||||
if (flags & BO_PINNED)
|
||||
msm_gem_unpin_locked(obj);
|
||||
|
||||
if (flags & BO_LOCKED)
|
||||
|
@ -273,7 +270,7 @@ static void submit_cleanup_bo(struct msm_gem_submit *submit, int i,
|
|||
|
||||
static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i)
|
||||
{
|
||||
unsigned cleanup_flags = BO_VMA_PINNED | BO_OBJ_PINNED | BO_LOCKED;
|
||||
unsigned cleanup_flags = BO_PINNED | BO_LOCKED;
|
||||
submit_cleanup_bo(submit, i, cleanup_flags);
|
||||
|
||||
if (!(submit->bos[i].flags & BO_VALID))
|
||||
|
@ -287,7 +284,7 @@ static int submit_lock_objects(struct msm_gem_submit *submit)
|
|||
|
||||
retry:
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
|
||||
if (slow_locked == i)
|
||||
slow_locked = -1;
|
||||
|
@ -295,7 +292,7 @@ retry:
|
|||
contended = i;
|
||||
|
||||
if (!(submit->bos[i].flags & BO_LOCKED)) {
|
||||
ret = dma_resv_lock_interruptible(msm_obj->base.resv,
|
||||
ret = dma_resv_lock_interruptible(obj->resv,
|
||||
&submit->ticket);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
@ -321,9 +318,9 @@ fail:
|
|||
submit_unlock_unpin_bo(submit, slow_locked);
|
||||
|
||||
if (ret == -EDEADLK) {
|
||||
struct msm_gem_object *msm_obj = submit->bos[contended].obj;
|
||||
struct drm_gem_object *obj = submit->bos[contended].obj;
|
||||
/* we lost out in a seqno race, lock and retry.. */
|
||||
ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv,
|
||||
ret = dma_resv_lock_slow_interruptible(obj->resv,
|
||||
&submit->ticket);
|
||||
if (!ret) {
|
||||
submit->bos[contended].flags |= BO_LOCKED;
|
||||
|
@ -346,7 +343,7 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
|
|||
int i, ret = 0;
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct drm_gem_object *obj = &submit->bos[i].obj->base;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
bool write = submit->bos[i].flags & MSM_SUBMIT_BO_WRITE;
|
||||
|
||||
/* NOTE: _reserve_shared() must happen before
|
||||
|
@ -384,12 +381,13 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
|
|||
|
||||
static int submit_pin_objects(struct msm_gem_submit *submit)
|
||||
{
|
||||
struct msm_drm_private *priv = submit->dev->dev_private;
|
||||
int i, ret = 0;
|
||||
|
||||
submit->valid = true;
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct drm_gem_object *obj = &submit->bos[i].obj->base;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
struct msm_gem_vma *vma;
|
||||
|
||||
/* if locking succeeded, pin bo: */
|
||||
|
@ -403,9 +401,6 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
|
|||
if (ret)
|
||||
break;
|
||||
|
||||
submit->bos[i].flags |= BO_OBJ_PINNED | BO_VMA_PINNED;
|
||||
submit->bos[i].vma = vma;
|
||||
|
||||
if (vma->iova == submit->bos[i].iova) {
|
||||
submit->bos[i].flags |= BO_VALID;
|
||||
} else {
|
||||
|
@ -416,6 +411,20 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* A second loop while holding the LRU lock (a) avoids acquiring/dropping
|
||||
* the LRU lock for each individual bo, while (b) avoiding holding the
|
||||
* LRU lock while calling msm_gem_pin_vma_locked() (which could trigger
|
||||
* get_pages() which could trigger reclaim.. and if we held the LRU lock
|
||||
* could trigger deadlock with the shrinker).
|
||||
*/
|
||||
mutex_lock(&priv->lru.lock);
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
msm_gem_pin_obj_locked(submit->bos[i].obj);
|
||||
submit->bos[i].flags |= BO_PINNED;
|
||||
}
|
||||
mutex_unlock(&priv->lru.lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -424,7 +433,7 @@ static void submit_attach_object_fences(struct msm_gem_submit *submit)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct drm_gem_object *obj = &submit->bos[i].obj->base;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
|
||||
if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
|
||||
dma_resv_add_fence(obj->resv, submit->user_fence,
|
||||
|
@ -436,7 +445,7 @@ static void submit_attach_object_fences(struct msm_gem_submit *submit)
|
|||
}
|
||||
|
||||
static int submit_bo(struct msm_gem_submit *submit, uint32_t idx,
|
||||
struct msm_gem_object **obj, uint64_t *iova, bool *valid)
|
||||
struct drm_gem_object **obj, uint64_t *iova, bool *valid)
|
||||
{
|
||||
if (idx >= submit->nr_bos) {
|
||||
DRM_ERROR("invalid buffer index: %u (out of %u)\n",
|
||||
|
@ -455,7 +464,7 @@ static int submit_bo(struct msm_gem_submit *submit, uint32_t idx,
|
|||
}
|
||||
|
||||
/* process the reloc's and patch up the cmdstream as needed: */
|
||||
static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *obj,
|
||||
static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *obj,
|
||||
uint32_t offset, uint32_t nr_relocs, struct drm_msm_gem_submit_reloc *relocs)
|
||||
{
|
||||
uint32_t i, last_offset = 0;
|
||||
|
@ -473,7 +482,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob
|
|||
/* For now, just map the entire thing. Eventually we probably
|
||||
* to do it page-by-page, w/ kmap() if not vmap()d..
|
||||
*/
|
||||
ptr = msm_gem_get_vaddr_locked(&obj->base);
|
||||
ptr = msm_gem_get_vaddr_locked(obj);
|
||||
|
||||
if (IS_ERR(ptr)) {
|
||||
ret = PTR_ERR(ptr);
|
||||
|
@ -497,7 +506,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob
|
|||
/* offset in dwords: */
|
||||
off = submit_reloc.submit_offset / 4;
|
||||
|
||||
if ((off >= (obj->base.size / 4)) ||
|
||||
if ((off >= (obj->size / 4)) ||
|
||||
(off < last_offset)) {
|
||||
DRM_ERROR("invalid offset %u at reloc %u\n", off, i);
|
||||
ret = -EINVAL;
|
||||
|
@ -524,7 +533,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob
|
|||
}
|
||||
|
||||
out:
|
||||
msm_gem_put_vaddr_locked(&obj->base);
|
||||
msm_gem_put_vaddr_locked(obj);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -539,13 +548,13 @@ static void submit_cleanup(struct msm_gem_submit *submit, bool error)
|
|||
unsigned i;
|
||||
|
||||
if (error)
|
||||
cleanup_flags |= BO_VMA_PINNED | BO_OBJ_PINNED;
|
||||
cleanup_flags |= BO_PINNED;
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
submit_cleanup_bo(submit, i, cleanup_flags);
|
||||
if (error)
|
||||
drm_gem_object_put(&msm_obj->base);
|
||||
drm_gem_object_put(obj);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -554,7 +563,7 @@ void msm_submit_retire(struct msm_gem_submit *submit)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct drm_gem_object *obj = &submit->bos[i].obj->base;
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
|
||||
drm_gem_object_put(obj);
|
||||
}
|
||||
|
@ -861,17 +870,17 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
|
|||
goto out;
|
||||
|
||||
for (i = 0; i < args->nr_cmds; i++) {
|
||||
struct msm_gem_object *msm_obj;
|
||||
struct drm_gem_object *obj;
|
||||
uint64_t iova;
|
||||
|
||||
ret = submit_bo(submit, submit->cmd[i].idx,
|
||||
&msm_obj, &iova, NULL);
|
||||
&obj, &iova, NULL);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (!submit->cmd[i].size ||
|
||||
((submit->cmd[i].size + submit->cmd[i].offset) >
|
||||
msm_obj->base.size / 4)) {
|
||||
obj->size / 4)) {
|
||||
DRM_ERROR("invalid cmdstream size: %u\n", submit->cmd[i].size * 4);
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
|
@ -882,7 +891,17 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
|
|||
if (submit->valid)
|
||||
continue;
|
||||
|
||||
ret = submit_reloc(submit, msm_obj, submit->cmd[i].offset * 4,
|
||||
if (!gpu->allow_relocs) {
|
||||
if (submit->cmd[i].nr_relocs) {
|
||||
DRM_ERROR("relocs not allowed\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = submit_reloc(submit, obj, submit->cmd[i].offset * 4,
|
||||
submit->cmd[i].nr_relocs, submit->cmd[i].relocs);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
|
|
@ -38,41 +38,12 @@ msm_gem_address_space_get(struct msm_gem_address_space *aspace)
|
|||
return aspace;
|
||||
}
|
||||
|
||||
bool msm_gem_vma_inuse(struct msm_gem_vma *vma)
|
||||
{
|
||||
bool ret = true;
|
||||
|
||||
spin_lock(&vma->lock);
|
||||
|
||||
if (vma->inuse > 0)
|
||||
goto out;
|
||||
|
||||
while (vma->fence_mask) {
|
||||
unsigned idx = ffs(vma->fence_mask) - 1;
|
||||
|
||||
if (!msm_fence_completed(vma->fctx[idx], vma->fence[idx]))
|
||||
goto out;
|
||||
|
||||
vma->fence_mask &= ~BIT(idx);
|
||||
}
|
||||
|
||||
ret = false;
|
||||
|
||||
out:
|
||||
spin_unlock(&vma->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Actually unmap memory for the vma */
|
||||
void msm_gem_vma_purge(struct msm_gem_vma *vma)
|
||||
{
|
||||
struct msm_gem_address_space *aspace = vma->aspace;
|
||||
unsigned size = vma->node.size;
|
||||
|
||||
/* Print a message if we try to purge a vma in use */
|
||||
GEM_WARN_ON(msm_gem_vma_inuse(vma));
|
||||
|
||||
/* Don't do anything if the memory isn't mapped */
|
||||
if (!vma->mapped)
|
||||
return;
|
||||
|
@ -82,33 +53,6 @@ void msm_gem_vma_purge(struct msm_gem_vma *vma)
|
|||
vma->mapped = false;
|
||||
}
|
||||
|
||||
static void vma_unpin_locked(struct msm_gem_vma *vma)
|
||||
{
|
||||
if (GEM_WARN_ON(!vma->inuse))
|
||||
return;
|
||||
if (!GEM_WARN_ON(!vma->iova))
|
||||
vma->inuse--;
|
||||
}
|
||||
|
||||
/* Remove reference counts for the mapping */
|
||||
void msm_gem_vma_unpin(struct msm_gem_vma *vma)
|
||||
{
|
||||
spin_lock(&vma->lock);
|
||||
vma_unpin_locked(vma);
|
||||
spin_unlock(&vma->lock);
|
||||
}
|
||||
|
||||
/* Replace pin reference with fence: */
|
||||
void msm_gem_vma_unpin_fenced(struct msm_gem_vma *vma, struct msm_fence_context *fctx)
|
||||
{
|
||||
spin_lock(&vma->lock);
|
||||
vma->fctx[fctx->index] = fctx;
|
||||
vma->fence[fctx->index] = fctx->last_fence;
|
||||
vma->fence_mask |= BIT(fctx->index);
|
||||
vma_unpin_locked(vma);
|
||||
spin_unlock(&vma->lock);
|
||||
}
|
||||
|
||||
/* Map and pin vma: */
|
||||
int
|
||||
msm_gem_vma_map(struct msm_gem_vma *vma, int prot,
|
||||
|
@ -120,11 +64,6 @@ msm_gem_vma_map(struct msm_gem_vma *vma, int prot,
|
|||
if (GEM_WARN_ON(!vma->iova))
|
||||
return -EINVAL;
|
||||
|
||||
/* Increase the usage counter */
|
||||
spin_lock(&vma->lock);
|
||||
vma->inuse++;
|
||||
spin_unlock(&vma->lock);
|
||||
|
||||
if (vma->mapped)
|
||||
return 0;
|
||||
|
||||
|
@ -146,9 +85,6 @@ msm_gem_vma_map(struct msm_gem_vma *vma, int prot,
|
|||
|
||||
if (ret) {
|
||||
vma->mapped = false;
|
||||
spin_lock(&vma->lock);
|
||||
vma->inuse--;
|
||||
spin_unlock(&vma->lock);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
@ -159,7 +95,7 @@ void msm_gem_vma_close(struct msm_gem_vma *vma)
|
|||
{
|
||||
struct msm_gem_address_space *aspace = vma->aspace;
|
||||
|
||||
GEM_WARN_ON(msm_gem_vma_inuse(vma) || vma->mapped);
|
||||
GEM_WARN_ON(vma->mapped);
|
||||
|
||||
spin_lock(&aspace->lock);
|
||||
if (vma->iova)
|
||||
|
@ -179,7 +115,6 @@ struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_address_space *aspace)
|
|||
if (!vma)
|
||||
return NULL;
|
||||
|
||||
spin_lock_init(&vma->lock);
|
||||
vma->aspace = aspace;
|
||||
|
||||
return vma;
|
||||
|
|
|
@ -219,36 +219,36 @@ static void msm_gpu_devcoredump_free(void *data)
|
|||
}
|
||||
|
||||
static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
|
||||
struct msm_gem_object *obj, u64 iova, bool full)
|
||||
struct drm_gem_object *obj, u64 iova, bool full)
|
||||
{
|
||||
struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
|
||||
|
||||
/* Don't record write only objects */
|
||||
state_bo->size = obj->base.size;
|
||||
state_bo->size = obj->size;
|
||||
state_bo->iova = iova;
|
||||
|
||||
BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(obj->name));
|
||||
BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(to_msm_bo(obj)->name));
|
||||
|
||||
memcpy(state_bo->name, obj->name, sizeof(state_bo->name));
|
||||
memcpy(state_bo->name, to_msm_bo(obj)->name, sizeof(state_bo->name));
|
||||
|
||||
if (full) {
|
||||
void *ptr;
|
||||
|
||||
state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
|
||||
state_bo->data = kvmalloc(obj->size, GFP_KERNEL);
|
||||
if (!state_bo->data)
|
||||
goto out;
|
||||
|
||||
msm_gem_lock(&obj->base);
|
||||
ptr = msm_gem_get_vaddr_active(&obj->base);
|
||||
msm_gem_unlock(&obj->base);
|
||||
msm_gem_lock(obj);
|
||||
ptr = msm_gem_get_vaddr_active(obj);
|
||||
msm_gem_unlock(obj);
|
||||
if (IS_ERR(ptr)) {
|
||||
kvfree(state_bo->data);
|
||||
state_bo->data = NULL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
memcpy(state_bo->data, ptr, obj->base.size);
|
||||
msm_gem_put_vaddr(&obj->base);
|
||||
memcpy(state_bo->data, ptr, obj->size);
|
||||
msm_gem_put_vaddr(obj);
|
||||
}
|
||||
out:
|
||||
state->nr_bos++;
|
||||
|
@ -749,13 +749,11 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
struct msm_ringbuffer *ring = submit->ring;
|
||||
unsigned long flags;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&gpu->lock));
|
||||
|
||||
pm_runtime_get_sync(&gpu->pdev->dev);
|
||||
|
||||
msm_gpu_hw_init(gpu);
|
||||
mutex_lock(&gpu->lock);
|
||||
|
||||
submit->seqno = submit->hw_fence->seqno;
|
||||
msm_gpu_hw_init(gpu);
|
||||
|
||||
update_sw_cntrs(gpu);
|
||||
|
||||
|
@ -781,8 +779,11 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
gpu->funcs->submit(gpu, submit);
|
||||
gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
|
||||
|
||||
pm_runtime_put(&gpu->pdev->dev);
|
||||
hangcheck_timer_reset(gpu);
|
||||
|
||||
mutex_unlock(&gpu->lock);
|
||||
|
||||
pm_runtime_put(&gpu->pdev->dev);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -897,7 +898,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
gpu->irq = platform_get_irq(pdev, 0);
|
||||
if (gpu->irq < 0) {
|
||||
ret = gpu->irq;
|
||||
DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
|
|
@ -285,6 +285,15 @@ struct msm_gpu {
|
|||
/* True if the hardware supports expanded apriv (a650 and newer) */
|
||||
bool hw_apriv;
|
||||
|
||||
/**
|
||||
* @allow_relocs: allow relocs in SUBMIT ioctl
|
||||
*
|
||||
* Mesa won't use relocs for driver version 1.4.0 and later. This
|
||||
* switch-over happened early enough in mesa a6xx bringup that we
|
||||
* can disallow relocs for a6xx and newer.
|
||||
*/
|
||||
bool allow_relocs;
|
||||
|
||||
struct thermal_cooling_device *cooling;
|
||||
};
|
||||
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
#include <linux/pm_runtime.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
#include "msm_drv.h"
|
||||
#include "msm_mdss.h"
|
||||
#include "msm_kms.h"
|
||||
|
||||
#define HW_REV 0x0
|
||||
|
@ -28,16 +28,6 @@
|
|||
|
||||
#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
|
||||
|
||||
struct msm_mdss_data {
|
||||
u32 ubwc_version;
|
||||
/* can be read from register 0x58 */
|
||||
u32 ubwc_dec_version;
|
||||
u32 ubwc_swizzle;
|
||||
u32 ubwc_static;
|
||||
u32 highest_bank_bit;
|
||||
u32 macrotile_mode;
|
||||
};
|
||||
|
||||
struct msm_mdss {
|
||||
struct device *dev;
|
||||
|
||||
|
@ -187,12 +177,6 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#define UBWC_1_0 0x10000000
|
||||
#define UBWC_2_0 0x20000000
|
||||
#define UBWC_3_0 0x30000000
|
||||
#define UBWC_4_0 0x40000000
|
||||
#define UBWC_4_3 0x40030000
|
||||
|
||||
static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
|
||||
{
|
||||
const struct msm_mdss_data *data = msm_mdss->mdss_data;
|
||||
|
@ -207,10 +191,10 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
|
|||
(data->highest_bank_bit & 0x3) << 4 |
|
||||
(data->macrotile_mode & 0x1) << 12;
|
||||
|
||||
if (data->ubwc_version == UBWC_3_0)
|
||||
if (data->ubwc_enc_version == UBWC_3_0)
|
||||
value |= BIT(10);
|
||||
|
||||
if (data->ubwc_version == UBWC_1_0)
|
||||
if (data->ubwc_enc_version == UBWC_1_0)
|
||||
value |= BIT(8);
|
||||
|
||||
writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
|
||||
|
@ -226,7 +210,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
|
|||
|
||||
writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
|
||||
|
||||
if (data->ubwc_version == UBWC_3_0) {
|
||||
if (data->ubwc_enc_version == UBWC_3_0) {
|
||||
writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
|
||||
writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
|
||||
} else {
|
||||
|
@ -238,6 +222,18 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
|
|||
}
|
||||
}
|
||||
|
||||
const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
|
||||
{
|
||||
struct msm_mdss *mdss;
|
||||
|
||||
if (!dev)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
mdss = dev_get_drvdata(dev);
|
||||
|
||||
return mdss->mdss_data;
|
||||
}
|
||||
|
||||
static int msm_mdss_enable(struct msm_mdss *msm_mdss)
|
||||
{
|
||||
int ret;
|
||||
|
@ -270,6 +266,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
|
|||
* UBWC_n and the rest of params comes from hw data.
|
||||
*/
|
||||
switch (msm_mdss->mdss_data->ubwc_dec_version) {
|
||||
case 0: /* no UBWC */
|
||||
case UBWC_1_0:
|
||||
/* do nothing */
|
||||
break;
|
||||
case UBWC_2_0:
|
||||
msm_mdss_setup_ubwc_dec_20(msm_mdss);
|
||||
break;
|
||||
|
@ -508,14 +508,26 @@ static int mdss_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct msm_mdss_data msm8998_data = {
|
||||
.ubwc_enc_version = UBWC_1_0,
|
||||
.ubwc_dec_version = UBWC_1_0,
|
||||
.highest_bank_bit = 1,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data qcm2290_data = {
|
||||
/* no UBWC */
|
||||
.highest_bank_bit = 0x2,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sc7180_data = {
|
||||
.ubwc_version = UBWC_2_0,
|
||||
.ubwc_enc_version = UBWC_2_0,
|
||||
.ubwc_dec_version = UBWC_2_0,
|
||||
.ubwc_static = 0x1e,
|
||||
.highest_bank_bit = 0x3,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sc7280_data = {
|
||||
.ubwc_version = UBWC_3_0,
|
||||
.ubwc_enc_version = UBWC_3_0,
|
||||
.ubwc_dec_version = UBWC_4_0,
|
||||
.ubwc_swizzle = 6,
|
||||
.ubwc_static = 1,
|
||||
|
@ -524,14 +536,14 @@ static const struct msm_mdss_data sc7280_data = {
|
|||
};
|
||||
|
||||
static const struct msm_mdss_data sc8180x_data = {
|
||||
.ubwc_version = UBWC_3_0,
|
||||
.ubwc_enc_version = UBWC_3_0,
|
||||
.ubwc_dec_version = UBWC_3_0,
|
||||
.highest_bank_bit = 3,
|
||||
.macrotile_mode = 1,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sc8280xp_data = {
|
||||
.ubwc_version = UBWC_4_0,
|
||||
.ubwc_enc_version = UBWC_4_0,
|
||||
.ubwc_dec_version = UBWC_4_0,
|
||||
.ubwc_swizzle = 6,
|
||||
.ubwc_static = 1,
|
||||
|
@ -540,13 +552,13 @@ static const struct msm_mdss_data sc8280xp_data = {
|
|||
};
|
||||
|
||||
static const struct msm_mdss_data sdm845_data = {
|
||||
.ubwc_version = UBWC_2_0,
|
||||
.ubwc_enc_version = UBWC_2_0,
|
||||
.ubwc_dec_version = UBWC_2_0,
|
||||
.highest_bank_bit = 2,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sm6350_data = {
|
||||
.ubwc_version = UBWC_2_0,
|
||||
.ubwc_enc_version = UBWC_2_0,
|
||||
.ubwc_dec_version = UBWC_2_0,
|
||||
.ubwc_swizzle = 6,
|
||||
.ubwc_static = 0x1e,
|
||||
|
@ -554,20 +566,28 @@ static const struct msm_mdss_data sm6350_data = {
|
|||
};
|
||||
|
||||
static const struct msm_mdss_data sm8150_data = {
|
||||
.ubwc_version = UBWC_3_0,
|
||||
.ubwc_enc_version = UBWC_3_0,
|
||||
.ubwc_dec_version = UBWC_3_0,
|
||||
.highest_bank_bit = 2,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sm6115_data = {
|
||||
.ubwc_version = UBWC_1_0,
|
||||
.ubwc_enc_version = UBWC_1_0,
|
||||
.ubwc_dec_version = UBWC_2_0,
|
||||
.ubwc_swizzle = 7,
|
||||
.ubwc_static = 0x11f,
|
||||
.highest_bank_bit = 0x1,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sm6125_data = {
|
||||
.ubwc_enc_version = UBWC_1_0,
|
||||
.ubwc_dec_version = UBWC_3_0,
|
||||
.ubwc_swizzle = 1,
|
||||
.highest_bank_bit = 1,
|
||||
};
|
||||
|
||||
static const struct msm_mdss_data sm8250_data = {
|
||||
.ubwc_version = UBWC_4_0,
|
||||
.ubwc_enc_version = UBWC_4_0,
|
||||
.ubwc_dec_version = UBWC_4_0,
|
||||
.ubwc_swizzle = 6,
|
||||
.ubwc_static = 1,
|
||||
|
@ -577,7 +597,7 @@ static const struct msm_mdss_data sm8250_data = {
|
|||
};
|
||||
|
||||
static const struct msm_mdss_data sm8550_data = {
|
||||
.ubwc_version = UBWC_4_0,
|
||||
.ubwc_enc_version = UBWC_4_0,
|
||||
.ubwc_dec_version = UBWC_4_3,
|
||||
.ubwc_swizzle = 6,
|
||||
.ubwc_static = 1,
|
||||
|
@ -585,17 +605,17 @@ static const struct msm_mdss_data sm8550_data = {
|
|||
.highest_bank_bit = 3,
|
||||
.macrotile_mode = 1,
|
||||
};
|
||||
|
||||
static const struct of_device_id mdss_dt_match[] = {
|
||||
{ .compatible = "qcom,mdss" },
|
||||
{ .compatible = "qcom,msm8998-mdss" },
|
||||
{ .compatible = "qcom,qcm2290-mdss" },
|
||||
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
|
||||
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
|
||||
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
|
||||
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
|
||||
{ .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
|
||||
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
|
||||
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
|
||||
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
|
||||
{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
|
||||
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
|
||||
{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
|
||||
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
|
||||
|
|
|
@ -0,0 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation
|
||||
*/
|
||||
|
||||
#ifndef __MSM_MDSS_H__
|
||||
#define __MSM_MDSS_H__
|
||||
|
||||
struct msm_mdss_data {
|
||||
u32 ubwc_enc_version;
|
||||
/* can be read from register 0x58 */
|
||||
u32 ubwc_dec_version;
|
||||
u32 ubwc_swizzle;
|
||||
u32 ubwc_static;
|
||||
u32 highest_bank_bit;
|
||||
u32 macrotile_mode;
|
||||
};
|
||||
|
||||
#define UBWC_1_0 0x10000000
|
||||
#define UBWC_2_0 0x20000000
|
||||
#define UBWC_3_0 0x30000000
|
||||
#define UBWC_4_0 0x40000000
|
||||
#define UBWC_4_3 0x40030000
|
||||
|
||||
const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev);
|
||||
|
||||
#endif /* __MSM_MDSS_H__ */
|
|
@ -310,7 +310,7 @@ static void snapshot_buf(struct msm_rd_state *rd,
|
|||
struct msm_gem_submit *submit, int idx,
|
||||
uint64_t iova, uint32_t size, bool full)
|
||||
{
|
||||
struct msm_gem_object *obj = submit->bos[idx].obj;
|
||||
struct drm_gem_object *obj = submit->bos[idx].obj;
|
||||
unsigned offset = 0;
|
||||
const char *buf;
|
||||
|
||||
|
@ -318,7 +318,7 @@ static void snapshot_buf(struct msm_rd_state *rd,
|
|||
offset = iova - submit->bos[idx].iova;
|
||||
} else {
|
||||
iova = submit->bos[idx].iova;
|
||||
size = obj->base.size;
|
||||
size = obj->size;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -335,7 +335,7 @@ static void snapshot_buf(struct msm_rd_state *rd,
|
|||
if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ))
|
||||
return;
|
||||
|
||||
buf = msm_gem_get_vaddr_active(&obj->base);
|
||||
buf = msm_gem_get_vaddr_active(obj);
|
||||
if (IS_ERR(buf))
|
||||
return;
|
||||
|
||||
|
@ -343,7 +343,7 @@ static void snapshot_buf(struct msm_rd_state *rd,
|
|||
|
||||
rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
|
||||
|
||||
msm_gem_put_vaddr_locked(&obj->base);
|
||||
msm_gem_put_vaddr_locked(obj);
|
||||
}
|
||||
|
||||
/* called under gpu->lock */
|
||||
|
|
|
@ -16,25 +16,26 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job)
|
|||
struct msm_gem_submit *submit = to_msm_submit(job);
|
||||
struct msm_fence_context *fctx = submit->ring->fctx;
|
||||
struct msm_gpu *gpu = submit->gpu;
|
||||
struct msm_drm_private *priv = gpu->dev->dev_private;
|
||||
int i;
|
||||
|
||||
msm_fence_init(submit->hw_fence, fctx);
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct drm_gem_object *obj = &submit->bos[i].obj->base;
|
||||
submit->seqno = submit->hw_fence->seqno;
|
||||
|
||||
mutex_lock(&priv->lru.lock);
|
||||
|
||||
for (i = 0; i < submit->nr_bos; i++) {
|
||||
struct drm_gem_object *obj = submit->bos[i].obj;
|
||||
|
||||
msm_gem_vma_unpin_fenced(submit->bos[i].vma, fctx);
|
||||
msm_gem_unpin_active(obj);
|
||||
submit->bos[i].flags &= ~(BO_VMA_PINNED | BO_OBJ_PINNED);
|
||||
submit->bos[i].flags &= ~BO_PINNED;
|
||||
}
|
||||
|
||||
/* TODO move submit path over to using a per-ring lock.. */
|
||||
mutex_lock(&gpu->lock);
|
||||
mutex_unlock(&priv->lru.lock);
|
||||
|
||||
msm_gpu_submit(gpu, submit);
|
||||
|
||||
mutex_unlock(&gpu->lock);
|
||||
|
||||
return dma_fence_get(submit->hw_fence);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue