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clk: at91: sam9x60-pll: check fcore against ranges
According to datasheet the range of 600-1200MHz is for the
frequency generated by the fractional part of the PLL (namely
Fcorepllck according to datasheet). With this in mind the output
range of the PLL itself (fractional + div), taking into account
that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.
Fixes: a436c2a447
("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
1bef0986b1
commit
390227dca8
2 changed files with 12 additions and 2 deletions
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@ -21,6 +21,9 @@
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#define UPLL_DIV 2
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#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
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#define FCORE_MIN (600000000)
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#define FCORE_MAX (1200000000)
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#define PLL_MAX_ID 1
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struct sam9x60_pll {
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@ -168,6 +171,7 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
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unsigned long bestdiv = 0;
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unsigned long bestmul = 0;
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unsigned long bestfrac = 0;
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u64 fcore = 0;
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if (rate < characteristics->output[0].min ||
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rate > characteristics->output[0].max)
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@ -212,6 +216,11 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
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remainder = rate - tmprate;
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}
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fcore = parent_rate * (tmpmul + 1) +
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((u64)parent_rate * tmpfrac >> 22);
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if (fcore < FCORE_MIN || fcore > FCORE_MAX)
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continue;
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/*
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* Compare the remainder with the best remainder found until
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* now and elect a new best multiplier/divider pair if the
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@ -231,7 +240,8 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
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}
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/* Check if bestrate is a valid output rate */
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if (bestrate < characteristics->output[0].min ||
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if (fcore < FCORE_MIN || fcore > FCORE_MAX ||
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bestrate < characteristics->output[0].min ||
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bestrate > characteristics->output[0].max)
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return -ERANGE;
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@ -22,7 +22,7 @@ static const struct clk_master_layout sam9x60_master_layout = {
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};
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static const struct clk_range plla_outputs[] = {
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{ .min = 300000000, .max = 600000000 },
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{ .min = 2343750, .max = 1200000000 },
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};
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static const struct clk_pll_characteristics plla_characteristics = {
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