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clk: at91: clk-sam9x60-pll: fix mul mask

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According to datasheet mul mask is on bits 31..24.

Fixes: a436c2a447 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Claudiu Beznea 2020-07-22 10:38:11 +03:00 committed by Stephen Boyd
parent 83331bfcc0
commit 3bf639a611
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/at91/clk-sam9x60-pll.c
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@ -15,7 +15,7 @@
#include "pmc.h"
#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
#define UPLL_DIV 2