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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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General RK3399 gets Mipi nodes, fixes for usb3 support and better support
for the type-c phys. The Kevin Chromebooks based on rk3399 now can use their internal edp displays. RK3328 gets its efuse node and Mali450 gpu node, which actually produces already some nice results with the WIP Lima driver. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlo7/J4QHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgVogB/wNdimvRAq7DdpIXxzMxoIEB3jXZ1zJ2TVL Gxim5h0RizQGIoiV4CYkQG2CdB1HG4Updj4SW9GYMl004fklSA26fB64WFVDM0VR 8uqVxkyCgo2QzzQxsNDPrXvNv3WjbrFVe+pWebzUZ1RCkHBgeJA/o61vjdNdvwq3 jgnr0YDjYYU+9sqoq31SYe0vzvoDGPmE7+Mlmw3eAszQqV66sk0/50IKV5z4xx8e oyD4M0JpPhGyPMoaBIekzr4wjkrKbEeJ5VQy/afFAYJWzi8X+vABIH78kGl+9q76 AmEQxBWr0ZQSIPWTVofUzHzKX78gSt2Gts2kbaFXPzMbCn8xWcKM =C4Hu -----END PGP SIGNATURE----- Merge tag 'v4.16-rockchip-dts64-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "Rockchip dts64 changes for 4.16" from Heiko Stübner: General RK3399 gets Mipi nodes, fixes for usb3 support and better support for the type-c phys. The Kevin Chromebooks based on rk3399 now can use their internal edp displays. RK3328 gets its efuse node and Mali450 gpu node, which actually produces already some nice results with the WIP Lima driver. * tag 'v4.16-rockchip-dts64-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add efuse device node for RK3328 SoC arm64: dts: rockchip: add rk3328 mali gpu node dt-bindings: gpu: mali-utgard: add rockchip,rk3328-mali compatible arm64: dts: rockchip: add extcon nodes and enable tcphy rk3399-gru arm64: dts: rockchip: add usb3-phy otg-port support for rk3399 arm64: dts: rockchip: add reset property for dwc3 controllers on rk3399 arm64: dts: rockchip: add the aclk_usb3 clocks for USB3 on rk3399 arm64: dts: rockchip: add pd_usb3 power-domain node for rk3399 arm64: dts: rockchip: Enable edp disaplay on kevin arm64: dts: rockchip: update mipi cells for RK3399 arm64: dts: rockchip: add mipi_dsi1 support for rk3399 arm64: dts: rockchip: add rk3399 DSI0 reset
This commit is contained in:
Arnd Bergmann
commit
3c37b6d989
5 changed files with 195 additions and 9 deletions
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@ -17,6 +17,7 @@ Required properties:
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+ rockchip,rk3066-mali
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+ rockchip,rk3188-mali
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+ rockchip,rk3228-mali
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+ rockchip,rk3328-mali
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+ stericsson,db8500-mali
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- reg: Physical base address and length of the GPU registers
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@ -531,6 +531,31 @@ tsadc: tsadc@ff250000 {
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status = "disabled";
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};
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efuse: efuse@ff260000 {
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compatible = "rockchip,rk3328-efuse";
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reg = <0x0 0xff260000 0x0 0x50>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru SCLK_EFUSE>;
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clock-names = "pclk_efuse";
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rockchip,efuse-size = <0x20>;
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/* Data cells */
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efuse_id: id@7 {
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reg = <0x07 0x10>;
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};
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cpu_leakage: cpu-leakage@17 {
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reg = <0x17 0x1>;
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};
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logic_leakage: logic-leakage@19 {
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reg = <0x19 0x1>;
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};
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efuse_cpu_version: cpu-version@1a {
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reg = <0x1a 0x1>;
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bits = <3 3>;
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};
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};
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saradc: adc@ff280000 {
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compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
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reg = <0x0 0xff280000 0x0 0x100>;
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@ -543,6 +568,28 @@ saradc: adc@ff280000 {
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status = "disabled";
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};
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gpu: gpu@ff300000 {
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compatible = "rockchip,rk3328-mali", "arm,mali-450";
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reg = <0x0 0xff300000 0x0 0x40000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1";
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clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
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clock-names = "bus", "core";
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resets = <&cru SRST_GPU_A>;
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};
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h265e_mmu: iommu@ff330200 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff330200 0 0x100>;
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@ -93,6 +93,18 @@ backlight: backlight {
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pwm-delay-us = <10000>;
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};
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edp_panel: edp-panel {
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compatible = "sharp,lq123p1jx31", "simple-panel";
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backlight = <&backlight>;
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power-supply = <&pp3300_disp>;
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ports {
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panel_in_edp: endpoint {
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remote-endpoint = <&edp_out_panel>;
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};
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};
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};
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thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu {
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compatible = "murata,ncp15wb473";
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pullup-uv = <1800000>;
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@ -268,6 +280,23 @@ touchscreen@4b {
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};
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};
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&edp {
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status = "okay";
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ports {
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edp_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in_edp>;
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};
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};
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};
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};
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&ppvar_bigcpu_pwm {
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regulator-min-microvolt = <798674>;
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regulator-max-microvolt = <1302172>;
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@ -855,6 +855,20 @@ cros_ec_pwm: ec-pwm {
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compatible = "google,cros-ec-pwm";
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#pwm-cells = <1>;
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};
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usbc_extcon0: extcon@0 {
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compatible = "google,extcon-usbc-cros-ec";
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google,usb-port-id = <0>;
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#extcon-cells = <0>;
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};
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usbc_extcon1: extcon@1 {
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compatible = "google,extcon-usbc-cros-ec";
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google,usb-port-id = <1>;
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#extcon-cells = <0>;
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};
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};
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};
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@ -865,6 +879,16 @@ &tsadc {
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rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
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};
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&tcphy0 {
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status = "okay";
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extcon = <&usbc_extcon0>;
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};
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&tcphy1 {
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status = "okay";
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extcon = <&usbc_extcon1>;
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};
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&u2phy0 {
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status = "okay";
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};
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@ -911,6 +935,7 @@ &usb_host1_ohci {
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&usbdrd3_0 {
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status = "okay";
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extcon = <&usbc_extcon0>;
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};
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&usbdrd_dwc3_0 {
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@ -920,6 +945,7 @@ &usbdrd_dwc3_0 {
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&usbdrd3_1 {
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status = "okay";
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extcon = <&usbc_extcon1>;
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};
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&usbdrd_dwc3_1 {
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@ -927,6 +953,22 @@ &usbdrd_dwc3_1 {
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dr_mode = "host";
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};
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&vopb {
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status = "okay";
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};
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&vopb_mmu {
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status = "okay";
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};
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&vopl {
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status = "okay";
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};
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&vopl_mmu {
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status = "okay";
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};
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#include <arm/cros-ec-keyboard.dtsi>
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#include <arm/cros-ec-sbs.dtsi>
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@ -397,9 +397,13 @@ usbdrd3_0: usb@fe800000 {
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#size-cells = <2>;
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ranges;
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clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
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<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
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<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
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<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "grf_clk";
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"bus_clk", "aclk_usb3_rksoc_axi_perf",
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"aclk_usb3", "grf_clk";
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resets = <&cru SRST_A_USB3_OTG0>;
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reset-names = "usb3-otg";
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status = "disabled";
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usbdrd_dwc3_0: dwc3 {
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@ -407,14 +411,15 @@ usbdrd_dwc3_0: dwc3 {
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reg = <0x0 0xfe800000 0x0 0x100000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
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dr_mode = "otg";
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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phys = <&u2phy0_otg>, <&tcphy0_usb3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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power-domains = <&power RK3399_PD_USB3>;
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status = "disabled";
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};
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};
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@ -425,9 +430,13 @@ usbdrd3_1: usb@fe900000 {
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#size-cells = <2>;
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ranges;
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clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
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<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
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<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
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<&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "grf_clk";
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"bus_clk", "aclk_usb3_rksoc_axi_perf",
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"aclk_usb3", "grf_clk";
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resets = <&cru SRST_A_USB3_OTG1>;
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reset-names = "usb3-otg";
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status = "disabled";
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usbdrd_dwc3_1: dwc3 {
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@ -435,14 +444,15 @@ usbdrd_dwc3_1: dwc3 {
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reg = <0x0 0xfe900000 0x0 0x100000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
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dr_mode = "otg";
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phys = <&u2phy1_otg>;
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phy-names = "usb2-phy";
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phys = <&u2phy1_otg>, <&tcphy1_usb3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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power-domains = <&power RK3399_PD_USB3>;
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status = "disabled";
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};
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};
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@ -991,6 +1001,12 @@ pd_sdioaudio@RK3399_PD_SDIOAUDIO {
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clocks = <&cru HCLK_SDIO>;
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pm_qos = <&qos_sdioaudio>;
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};
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pd_usb3@RK3399_PD_USB3 {
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reg = <RK3399_PD_USB3>;
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clocks = <&cru ACLK_USB3>;
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pm_qos = <&qos_usb_otg0>,
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<&qos_usb_otg1>;
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};
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pd_vio@RK3399_PD_VIO {
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reg = <RK3399_PD_VIO>;
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#address-cells = <1>;
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@ -1526,6 +1542,11 @@ vopl_out_hdmi: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&hdmi_in_vopl>;
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};
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vopl_out_mipi1: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&mipi1_in_vopl>;
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};
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};
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};
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@ -1573,6 +1594,11 @@ vopb_out_hdmi: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&hdmi_in_vopb>;
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};
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vopb_out_mipi1: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&mipi1_in_vopb>;
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};
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};
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};
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@ -1648,11 +1674,17 @@ mipi_dsi: mipi@ff960000 {
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<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
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clock-names = "ref", "pclk", "phy_cfg", "grf";
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power-domains = <&power RK3399_PD_VIO>;
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resets = <&cru SRST_P_MIPI_DSI0>;
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reset-names = "apb";
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rockchip,grf = <&grf>;
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status = "disabled";
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ports {
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mipi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1668,6 +1700,41 @@ mipi_in_vopl: endpoint@1 {
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};
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};
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mipi_dsi1: mipi@ff968000 {
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compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
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reg = <0x0 0xff968000 0x0 0x8000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
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<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
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clock-names = "ref", "pclk", "phy_cfg", "grf";
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power-domains = <&power RK3399_PD_VIO>;
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resets = <&cru SRST_P_MIPI_DSI1>;
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reset-names = "apb";
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rockchip,grf = <&grf>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_mipi1>;
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};
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mipi1_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_mipi1>;
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};
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};
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};
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};
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edp: edp@ff970000 {
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compatible = "rockchip,rk3399-edp";
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reg = <0x0 0xff970000 0x0 0x8000>;
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Reference in a new issue