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spi: davinci: enable and power-up SPI only when required
Enable SPI only when active transfers are in progress. Keep it in local low power when not in use. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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3409e408ab
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3f27b57c16
1 changed files with 6 additions and 2 deletions
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@ -49,7 +49,6 @@
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#define SPIFMT_WDELAY_SHIFT 24
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
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@ -67,6 +66,7 @@
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/* SPIGCR1 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_POWERDOWN_MASK BIT(8)
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#define SPIGCR1_LOOPBACK_MASK BIT(16)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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@ -556,7 +556,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
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/* Enable SPI */
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clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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INIT_COMPLETION(davinci_spi->done);
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@ -693,6 +693,9 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
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}
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clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
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/*
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* Check for bit error, desync error,parity error,timeout error and
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* receive overflow errors
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@ -937,6 +940,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
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/* master mode default */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
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ret = spi_bitbang_start(&davinci_spi->bitbang);
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if (ret)
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