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drm/amd/display: Update panel register

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[Why]
Incorrect panel register settings are applied for power sequence because
the register macro is not defined in resource.

[How]
Implement same register space to future resource files.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chris Park 2020-10-19 14:32:14 -04:00 committed by Alex Deucher
parent 06722b37d1
commit 41fd932e1a
1 changed files with 1 additions and 0 deletions
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drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
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@ -521,6 +521,7 @@ static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
[id] = {\
LE_DCN301_REG_LIST(id), \
UNIPHY_DCN2_REG_LIST(phyid), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
}
static const struct dce110_aux_registers_shift aux_shift = {