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drm/i915: Extract skl_watermark.c
Pull all the skl+ watermark code (and the dbuf/sagv/ipc code since it's all sort of intertwined and I'm too lazy to think of a finer grained split right now) into its own file from the catch-all intel_pm.c. Also sneak in the s/dev_priv/i915/ rename while at it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908191646.20239-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
parent
55544b2811
commit
42a0d25649
16 changed files with 3579 additions and 3541 deletions
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@ -257,7 +257,8 @@ i915-y += \
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display/intel_vga.o \
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display/i9xx_plane.o \
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display/skl_scaler.o \
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display/skl_universal_plane.o
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display/skl_universal_plane.o \
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display/skl_watermark.o
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i915-$(CONFIG_ACPI) += \
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display/intel_acpi.o \
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display/intel_opregion.o
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@ -43,9 +43,9 @@
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#include "intel_display_types.h"
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#include "intel_fb.h"
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#include "intel_fb_pin.h"
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#include "intel_pm.h"
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#include "intel_sprite.h"
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#include "skl_scaler.h"
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#include "skl_watermark.h"
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static void intel_plane_state_reset(struct intel_plane_state *plane_state,
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struct intel_plane *plane)
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@ -5,15 +5,17 @@
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#include <drm/drm_atomic_state_helper.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_atomic.h"
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#include "intel_bw.h"
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#include "intel_cdclk.h"
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#include "intel_display_core.h"
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#include "intel_display_types.h"
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#include "skl_watermark.h"
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#include "intel_mchbar_regs.h"
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#include "intel_pcode.h"
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#include "intel_pm.h"
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/* Parameters for Qclk Geyserville (QGV) */
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struct intel_qgv_point {
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@ -20,9 +20,9 @@
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#include "intel_fb.h"
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#include "intel_fb_pin.h"
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#include "intel_frontbuffer.h"
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#include "intel_pm.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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#include "skl_watermark.h"
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/* Cursor formats */
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static const u32 intel_cursor_formats[] = {
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@ -119,6 +119,7 @@
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#include "i9xx_plane.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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#include "skl_watermark.h"
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#include "vlv_dsi.h"
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#include "vlv_dsi_pll.h"
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#include "vlv_dsi_regs.h"
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@ -26,6 +26,7 @@
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#include "intel_pm.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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#include "skl_watermark.h"
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static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
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{
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@ -19,8 +19,8 @@
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#include "intel_mchbar_regs.h"
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#include "intel_pch_refclk.h"
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#include "intel_pcode.h"
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#include "intel_pm.h"
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#include "intel_snps_phy.h"
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#include "skl_watermark.h"
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#include "vlv_sideband.h"
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#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
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@ -17,10 +17,10 @@
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#include "intel_dpll.h"
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#include "intel_hotplug.h"
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#include "intel_pcode.h"
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#include "intel_pm.h"
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#include "intel_pps.h"
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#include "intel_tc.h"
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#include "intel_vga.h"
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#include "skl_watermark.h"
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#include "vlv_sideband.h"
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#include "vlv_sideband_reg.h"
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@ -23,6 +23,7 @@
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#include "intel_modeset_setup.h"
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#include "intel_pch_display.h"
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#include "intel_pm.h"
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#include "skl_watermark.h"
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static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
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struct drm_modeset_acquire_ctx *ctx)
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@ -15,8 +15,8 @@
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#include "intel_display_types.h"
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#include "intel_fdi.h"
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#include "intel_modeset_verify.h"
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#include "intel_pm.h"
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#include "intel_snps_phy.h"
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#include "skl_watermark.h"
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/*
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* Cross check the actual hw state with our own modeset state tracking (and its
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@ -15,11 +15,11 @@
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#include "intel_display_types.h"
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#include "intel_fb.h"
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#include "intel_fbc.h"
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#include "intel_pm.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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#include "skl_watermark.h"
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#include "pxp/intel_pxp.h"
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static const u32 skl_plane_formats[] = {
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3470
drivers/gpu/drm/i915/display/skl_watermark.c
Normal file
3470
drivers/gpu/drm/i915/display/skl_watermark.c
Normal file
File diff suppressed because it is too large
Load diff
78
drivers/gpu/drm/i915/display/skl_watermark.h
Normal file
78
drivers/gpu/drm/i915/display/skl_watermark.h
Normal file
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@ -0,0 +1,78 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __SKL_WATERMARK_H__
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#define __SKL_WATERMARK_H__
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#include <linux/types.h>
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#include "intel_display.h"
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#include "intel_global_state.h"
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#include "intel_pm_types.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_bw_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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bool intel_can_enable_sagv(struct drm_i915_private *i915,
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const struct intel_bw_state *bw_state);
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u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
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const struct skl_ddb_entry *entry);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_wm_get_hw_state(struct drm_i915_private *i915);
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void skl_wm_sanitize(struct drm_i915_private *i915);
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void intel_wm_state_verify(struct intel_crtc *crtc,
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struct intel_crtc_state *new_crtc_state);
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void intel_enable_ipc(struct drm_i915_private *i915);
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void intel_init_ipc(struct drm_i915_private *i915);
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void skl_wm_init(struct drm_i915_private *i915);
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struct intel_dbuf_state {
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struct intel_global_state base;
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struct skl_ddb_entry ddb[I915_MAX_PIPES];
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unsigned int weight[I915_MAX_PIPES];
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u8 slices[I915_MAX_PIPES];
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u8 enabled_slices;
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u8 active_pipes;
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bool joined_mbus;
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};
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
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#define intel_atomic_get_old_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
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#define intel_atomic_get_new_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
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int intel_dbuf_init(struct drm_i915_private *i915);
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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void intel_mbus_dbox_update(struct intel_atomic_state *state);
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#endif /* __SKL_WATERMARK_H__ */
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@ -61,6 +61,7 @@
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#include "display/intel_pps.h"
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#include "display/intel_sprite.h"
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#include "display/intel_vga.h"
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#include "display/skl_watermark.h"
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#include "gem/i915_gem_context.h"
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#include "gem/i915_gem_create.h"
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File diff suppressed because it is too large
Load diff
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@ -8,22 +8,9 @@
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#include <linux/types.h>
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#include "display/intel_display.h"
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#include "display/intel_global_state.h"
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#include "i915_drv.h"
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struct drm_device;
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struct drm_i915_private;
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struct i915_request;
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struct intel_atomic_state;
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struct intel_bw_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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struct skl_ddb_entry;
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struct skl_pipe_wm;
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struct skl_wm_level;
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struct intel_plane_state;
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void intel_init_clock_gating(struct drm_i915_private *dev_priv);
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void intel_suspend_hw(struct drm_i915_private *dev_priv);
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void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void intel_wm_state_verify(struct intel_crtc *crtc,
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struct intel_crtc_state *new_crtc_state);
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
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void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
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u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
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const struct skl_ddb_entry *entry);
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void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
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void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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void skl_wm_sanitize(struct drm_i915_private *dev_priv);
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bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
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const struct intel_bw_state *bw_state);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
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void intel_init_ipc(struct drm_i915_private *dev_priv);
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void intel_enable_ipc(struct drm_i915_private *dev_priv);
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bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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void intel_print_wm_latency(struct drm_i915_private *dev_priv,
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const char *name, const u16 wm[]);
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bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
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struct intel_dbuf_state {
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struct intel_global_state base;
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struct skl_ddb_entry ddb[I915_MAX_PIPES];
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unsigned int weight[I915_MAX_PIPES];
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u8 slices[I915_MAX_PIPES];
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u8 enabled_slices;
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u8 active_pipes;
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bool joined_mbus;
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};
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
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#define intel_atomic_get_old_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
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#define intel_atomic_get_new_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
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int intel_dbuf_init(struct drm_i915_private *dev_priv);
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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void intel_mbus_dbox_update(struct intel_atomic_state *state);
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#endif /* __INTEL_PM_H__ */
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