mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-04 09:59:32 +00:00
drm/nouveau/tegra: merge platform setup from nouveau drm
The copyright header in nvkm/engine/device/platform.c has been replaced with the NVIDIA one from drm/nouveau_platform.c, as most of the actual code is now theirs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
340b0e7c50
commit
43a70661ea
9 changed files with 221 additions and 285 deletions
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@ -25,10 +25,13 @@
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/agp_backend.h>
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#include <linux/reset.h>
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#include <linux/iommu.h>
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#include <asm/unaligned.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#ifndef ioread32_native
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#ifdef __BIG_ENDIAN
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@ -139,8 +139,6 @@ struct nvkm_device {
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struct nvkm_sw *sw;
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struct nvkm_engine *vic;
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struct nvkm_engine *vp;
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struct nouveau_platform_gpu *gpu;
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};
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struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
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@ -1,11 +1,31 @@
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#ifndef __NVKM_DEVICE_TEGRA_H__
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#define __NVKM_DEVICE_TEGRA_H__
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#include <core/device.h>
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#include <core/mm.h>
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struct nvkm_device_tegra {
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struct nvkm_device device;
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struct platform_device *pdev;
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int irq;
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struct reset_control *rst;
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struct clk *clk;
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struct clk *clk_pwr;
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struct regulator *vdd;
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struct {
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/*
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* Protects accesses to mm from subsystems
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*/
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struct mutex mutex;
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struct nvkm_mm mm;
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struct iommu_domain *domain;
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unsigned long pgshift;
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} iommu;
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int gpu_speedo;
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};
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int nvkm_device_tegra_new(struct platform_device *,
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@ -19,234 +19,32 @@
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iommu.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#include "nouveau_drm.h"
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#include "nouveau_platform.h"
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static int nouveau_platform_power_up(struct nouveau_platform_gpu *gpu)
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{
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int err;
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err = regulator_enable(gpu->vdd);
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if (err)
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goto err_power;
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err = clk_prepare_enable(gpu->clk);
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if (err)
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goto err_clk;
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err = clk_prepare_enable(gpu->clk_pwr);
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if (err)
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goto err_clk_pwr;
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clk_set_rate(gpu->clk_pwr, 204000000);
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udelay(10);
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reset_control_assert(gpu->rst);
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udelay(10);
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err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
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if (err)
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goto err_clamp;
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udelay(10);
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reset_control_deassert(gpu->rst);
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udelay(10);
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return 0;
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err_clamp:
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clk_disable_unprepare(gpu->clk_pwr);
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err_clk_pwr:
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clk_disable_unprepare(gpu->clk);
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err_clk:
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regulator_disable(gpu->vdd);
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err_power:
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return err;
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}
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static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu)
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{
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int err;
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reset_control_assert(gpu->rst);
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udelay(10);
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clk_disable_unprepare(gpu->clk_pwr);
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clk_disable_unprepare(gpu->clk);
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udelay(10);
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err = regulator_disable(gpu->vdd);
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if (err)
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return err;
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return 0;
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}
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#if IS_ENABLED(CONFIG_IOMMU_API)
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static void nouveau_platform_probe_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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int err;
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unsigned long pgsize_bitmap;
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mutex_init(&gpu->iommu.mutex);
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if (iommu_present(&platform_bus_type)) {
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gpu->iommu.domain = iommu_domain_alloc(&platform_bus_type);
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if (IS_ERR(gpu->iommu.domain))
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goto error;
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/*
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* A IOMMU is only usable if it supports page sizes smaller
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* or equal to the system's PAGE_SIZE, with a preference if
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* both are equal.
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*/
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pgsize_bitmap = gpu->iommu.domain->ops->pgsize_bitmap;
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if (pgsize_bitmap & PAGE_SIZE) {
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gpu->iommu.pgshift = PAGE_SHIFT;
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} else {
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gpu->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
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if (gpu->iommu.pgshift == 0) {
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dev_warn(dev, "unsupported IOMMU page size\n");
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goto free_domain;
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}
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gpu->iommu.pgshift -= 1;
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}
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err = iommu_attach_device(gpu->iommu.domain, dev);
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if (err)
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goto free_domain;
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err = nvkm_mm_init(&gpu->iommu._mm, 0,
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(1ULL << 40) >> gpu->iommu.pgshift, 1);
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if (err)
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goto detach_device;
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gpu->iommu.mm = &gpu->iommu._mm;
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}
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return;
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detach_device:
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iommu_detach_device(gpu->iommu.domain, dev);
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free_domain:
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iommu_domain_free(gpu->iommu.domain);
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error:
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gpu->iommu.domain = NULL;
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gpu->iommu.pgshift = 0;
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dev_err(dev, "cannot initialize IOMMU MM\n");
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}
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static void nouveau_platform_remove_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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if (gpu->iommu.domain) {
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nvkm_mm_fini(&gpu->iommu._mm);
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iommu_detach_device(gpu->iommu.domain, dev);
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iommu_domain_free(gpu->iommu.domain);
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}
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}
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#else
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static void nouveau_platform_probe_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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}
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static void nouveau_platform_remove_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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}
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#endif
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static int nouveau_platform_probe(struct platform_device *pdev)
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{
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struct nouveau_platform_gpu *gpu;
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struct nvkm_device *device;
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struct drm_device *drm;
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int err;
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gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL);
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if (!gpu)
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return -ENOMEM;
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gpu->vdd = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(gpu->vdd))
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return PTR_ERR(gpu->vdd);
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gpu->rst = devm_reset_control_get(&pdev->dev, "gpu");
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if (IS_ERR(gpu->rst))
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return PTR_ERR(gpu->rst);
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gpu->clk = devm_clk_get(&pdev->dev, "gpu");
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if (IS_ERR(gpu->clk))
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return PTR_ERR(gpu->clk);
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gpu->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
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if (IS_ERR(gpu->clk_pwr))
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return PTR_ERR(gpu->clk_pwr);
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nouveau_platform_probe_iommu(&pdev->dev, gpu);
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err = nouveau_platform_power_up(gpu);
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if (err)
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return err;
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int ret;
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drm = nouveau_platform_device_create(pdev, &device);
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if (IS_ERR(drm)) {
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err = PTR_ERR(drm);
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goto power_down;
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if (IS_ERR(drm))
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return PTR_ERR(drm);
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ret = drm_dev_register(drm, 0);
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if (ret < 0) {
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drm_dev_unref(drm);
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return ret;
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}
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device->gpu = gpu;
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gpu->gpu_speedo = tegra_sku_info.gpu_speedo_value;
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err = drm_dev_register(drm, 0);
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if (err < 0)
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goto err_unref;
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return 0;
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err_unref:
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drm_dev_unref(drm);
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power_down:
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nouveau_platform_power_down(gpu);
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nouveau_platform_remove_iommu(&pdev->dev, gpu);
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return err;
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}
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static int nouveau_platform_remove(struct platform_device *pdev)
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{
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struct drm_device *drm_dev = platform_get_drvdata(pdev);
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struct nouveau_drm *drm = nouveau_drm(drm_dev);
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struct nvkm_device *device = nvxx_device(&drm->device);
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struct nouveau_platform_gpu *gpu = device->gpu;
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int err;
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nouveau_drm_device_remove(drm_dev);
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err = nouveau_platform_power_down(gpu);
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nouveau_platform_remove_iommu(&pdev->dev, gpu);
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return err;
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struct drm_device *dev = platform_get_drvdata(pdev);
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nouveau_drm_device_remove(dev);
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return 0;
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}
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#if IS_ENABLED(CONFIG_OF)
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@ -19,44 +19,9 @@
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NOUVEAU_PLATFORM_H__
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#define __NOUVEAU_PLATFORM_H__
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#include "core/device.h"
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#include "core/mm.h"
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struct reset_control;
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struct clk;
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struct regulator;
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struct iommu_domain;
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struct platform_driver;
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struct nouveau_platform_gpu {
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struct reset_control *rst;
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struct clk *clk;
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struct clk *clk_pwr;
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struct regulator *vdd;
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struct {
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/*
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* Protects accesses to mm from subsystems
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*/
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struct mutex mutex;
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struct nvkm_mm _mm;
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/*
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* Just points to _mm. We need this to avoid embedding
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* struct nvkm_mm in os.h
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*/
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struct nvkm_mm *mm;
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struct iommu_domain *domain;
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unsigned long pgshift;
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} iommu;
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int gpu_speedo;
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};
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#include "nouveau_drm.h"
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extern struct platform_driver nouveau_platform_driver;
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright 2015 Red Hat Inc.
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -14,17 +14,138 @@
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <core/tegra.h>
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#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
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#include "priv.h"
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static int
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nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
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{
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int ret;
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ret = regulator_enable(tdev->vdd);
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if (ret)
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goto err_power;
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ret = clk_prepare_enable(tdev->clk);
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if (ret)
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goto err_clk;
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ret = clk_prepare_enable(tdev->clk_pwr);
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if (ret)
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goto err_clk_pwr;
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clk_set_rate(tdev->clk_pwr, 204000000);
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udelay(10);
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reset_control_assert(tdev->rst);
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udelay(10);
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ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
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if (ret)
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goto err_clamp;
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udelay(10);
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reset_control_deassert(tdev->rst);
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udelay(10);
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return 0;
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err_clamp:
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clk_disable_unprepare(tdev->clk_pwr);
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err_clk_pwr:
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clk_disable_unprepare(tdev->clk);
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err_clk:
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regulator_disable(tdev->vdd);
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err_power:
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return ret;
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}
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static int
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nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
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{
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reset_control_assert(tdev->rst);
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udelay(10);
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clk_disable_unprepare(tdev->clk_pwr);
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clk_disable_unprepare(tdev->clk);
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udelay(10);
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|
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return regulator_disable(tdev->vdd);
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}
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static void
|
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nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev)
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{
|
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#if IS_ENABLED(CONFIG_IOMMU_API)
|
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struct device *dev = &tdev->pdev->dev;
|
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unsigned long pgsize_bitmap;
|
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int ret;
|
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|
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mutex_init(&tdev->iommu.mutex);
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|
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if (iommu_present(&platform_bus_type)) {
|
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tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type);
|
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if (IS_ERR(tdev->iommu.domain))
|
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goto error;
|
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|
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/*
|
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* A IOMMU is only usable if it supports page sizes smaller
|
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* or equal to the system's PAGE_SIZE, with a preference if
|
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* both are equal.
|
||||
*/
|
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pgsize_bitmap = tdev->iommu.domain->ops->pgsize_bitmap;
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if (pgsize_bitmap & PAGE_SIZE) {
|
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tdev->iommu.pgshift = PAGE_SHIFT;
|
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} else {
|
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tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
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if (tdev->iommu.pgshift == 0) {
|
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dev_warn(dev, "unsupported IOMMU page size\n");
|
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goto free_domain;
|
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}
|
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tdev->iommu.pgshift -= 1;
|
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}
|
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|
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ret = iommu_attach_device(tdev->iommu.domain, dev);
|
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if (ret)
|
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goto free_domain;
|
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|
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ret = nvkm_mm_init(&tdev->iommu.mm, 0,
|
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(1ULL << 40) >> tdev->iommu.pgshift, 1);
|
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if (ret)
|
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goto detach_device;
|
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}
|
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|
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return;
|
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|
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detach_device:
|
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iommu_detach_device(tdev->iommu.domain, dev);
|
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|
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free_domain:
|
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iommu_domain_free(tdev->iommu.domain);
|
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|
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error:
|
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tdev->iommu.domain = NULL;
|
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tdev->iommu.pgshift = 0;
|
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dev_err(dev, "cannot initialize IOMMU MM\n");
|
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#endif
|
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}
|
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|
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static void
|
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nvkm_device_tegra_remove_iommu(struct nvkm_device_tegra *tdev)
|
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{
|
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#if IS_ENABLED(CONFIG_IOMMU_API)
|
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if (tdev->iommu.domain) {
|
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nvkm_mm_fini(&tdev->iommu.mm);
|
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iommu_detach_device(tdev->iommu.domain, tdev->device.dev);
|
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iommu_domain_free(tdev->iommu.domain);
|
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}
|
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#endif
|
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}
|
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|
||||
static struct nvkm_device_tegra *
|
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nvkm_device_tegra(struct nvkm_device *device)
|
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{
|
||||
|
@ -95,9 +216,19 @@ nvkm_device_tegra_init(struct nvkm_device *device)
|
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return 0;
|
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}
|
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|
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static void *
|
||||
nvkm_device_tegra_dtor(struct nvkm_device *device)
|
||||
{
|
||||
struct nvkm_device_tegra *tdev = nvkm_device_tegra(device);
|
||||
nvkm_device_tegra_power_down(tdev);
|
||||
nvkm_device_tegra_remove_iommu(tdev);
|
||||
return tdev;
|
||||
}
|
||||
|
||||
static const struct nvkm_device_func
|
||||
nvkm_device_tegra_func = {
|
||||
.tegra = nvkm_device_tegra,
|
||||
.dtor = nvkm_device_tegra_dtor,
|
||||
.init = nvkm_device_tegra_init,
|
||||
.fini = nvkm_device_tegra_fini,
|
||||
.resource_addr = nvkm_device_tegra_resource_addr,
|
||||
|
@ -112,6 +243,7 @@ nvkm_device_tegra_new(struct platform_device *pdev,
|
|||
struct nvkm_device **pdevice)
|
||||
{
|
||||
struct nvkm_device_tegra *tdev;
|
||||
int ret;
|
||||
|
||||
if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
|
@ -119,10 +251,37 @@ nvkm_device_tegra_new(struct platform_device *pdev,
|
|||
tdev->pdev = pdev;
|
||||
tdev->irq = -1;
|
||||
|
||||
return nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev,
|
||||
NVKM_DEVICE_TEGRA, pdev->id, NULL,
|
||||
cfg, dbg, detect, mmio, subdev_mask,
|
||||
&tdev->device);
|
||||
tdev->vdd = devm_regulator_get(&pdev->dev, "vdd");
|
||||
if (IS_ERR(tdev->vdd))
|
||||
return PTR_ERR(tdev->vdd);
|
||||
|
||||
tdev->rst = devm_reset_control_get(&pdev->dev, "gpu");
|
||||
if (IS_ERR(tdev->rst))
|
||||
return PTR_ERR(tdev->rst);
|
||||
|
||||
tdev->clk = devm_clk_get(&pdev->dev, "gpu");
|
||||
if (IS_ERR(tdev->clk))
|
||||
return PTR_ERR(tdev->clk);
|
||||
|
||||
tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
|
||||
if (IS_ERR(tdev->clk_pwr))
|
||||
return PTR_ERR(tdev->clk_pwr);
|
||||
|
||||
nvkm_device_tegra_probe_iommu(tdev);
|
||||
|
||||
ret = nvkm_device_tegra_power_up(tdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
tdev->gpu_speedo = tegra_sku_info.gpu_speedo_value;
|
||||
ret = nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev,
|
||||
NVKM_DEVICE_TEGRA, pdev->id, NULL,
|
||||
cfg, dbg, detect, mmio, subdev_mask,
|
||||
&tdev->device);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int
|
||||
|
|
|
@ -25,12 +25,9 @@
|
|||
#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
|
||||
#include "priv.h"
|
||||
|
||||
#include <core/tegra.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <nouveau_platform.h>
|
||||
#endif
|
||||
|
||||
#define MHZ (1000 * 1000)
|
||||
|
||||
#define MASK(w) ((1 << w) - 1)
|
||||
|
@ -649,6 +646,7 @@ gk20a_clk = {
|
|||
int
|
||||
gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
|
||||
{
|
||||
struct nvkm_device_tegra *tdev = device->func->tegra(device);
|
||||
struct gk20a_clk *clk;
|
||||
int ret, i;
|
||||
|
||||
|
@ -663,7 +661,7 @@ gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
|
|||
}
|
||||
|
||||
clk->params = &gk20a_pllg_params;
|
||||
clk->parent_rate = clk_get_rate(device->gpu->clk);
|
||||
clk->parent_rate = clk_get_rate(tdev->clk);
|
||||
|
||||
ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base);
|
||||
nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n",
|
||||
|
|
|
@ -42,14 +42,9 @@
|
|||
|
||||
#include <core/memory.h>
|
||||
#include <core/mm.h>
|
||||
#include <core/tegra.h>
|
||||
#include <subdev/fb.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/dma-attrs.h>
|
||||
#include <linux/iommu.h>
|
||||
#include <nouveau_platform.h>
|
||||
#endif
|
||||
|
||||
#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory)
|
||||
|
||||
struct gk20a_instobj {
|
||||
|
@ -423,8 +418,9 @@ gk20a_instmem = {
|
|||
|
||||
int
|
||||
gk20a_instmem_new(struct nvkm_device *device, int index,
|
||||
struct nvkm_instmem **pimem)
|
||||
struct nvkm_instmem **pimem)
|
||||
{
|
||||
struct nvkm_device_tegra *tdev = device->func->tegra(device);
|
||||
struct gk20a_instmem *imem;
|
||||
|
||||
if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
|
||||
|
@ -433,11 +429,11 @@ gk20a_instmem_new(struct nvkm_device *device, int index,
|
|||
spin_lock_init(&imem->lock);
|
||||
*pimem = &imem->base;
|
||||
|
||||
if (device->gpu->iommu.domain) {
|
||||
imem->domain = device->gpu->iommu.domain;
|
||||
imem->mm = device->gpu->iommu.mm;
|
||||
imem->iommu_pgshift = device->gpu->iommu.pgshift;
|
||||
imem->mm_mutex = &device->gpu->iommu.mutex;
|
||||
if (tdev->iommu.domain) {
|
||||
imem->domain = tdev->iommu.domain;
|
||||
imem->mm = &tdev->iommu.mm;
|
||||
imem->iommu_pgshift = tdev->iommu.pgshift;
|
||||
imem->mm_mutex = &tdev->iommu.mutex;
|
||||
|
||||
nvkm_info(&imem->base.subdev, "using IOMMU\n");
|
||||
} else {
|
||||
|
|
|
@ -22,9 +22,7 @@
|
|||
#define gk20a_volt(p) container_of((p), struct gk20a_volt, base)
|
||||
#include "priv.h"
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <nouveau_platform.h>
|
||||
#endif
|
||||
#include <core/tegra.h>
|
||||
|
||||
struct cvb_coef {
|
||||
int c0;
|
||||
|
@ -159,6 +157,7 @@ gk20a_volt = {
|
|||
int
|
||||
gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
|
||||
{
|
||||
struct nvkm_device_tegra *tdev = device->func->tegra(device);
|
||||
struct gk20a_volt *volt;
|
||||
int i, uv;
|
||||
|
||||
|
@ -168,10 +167,10 @@ gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
|
|||
nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base);
|
||||
*pvolt = &volt->base;
|
||||
|
||||
uv = regulator_get_voltage(device->gpu->vdd);
|
||||
uv = regulator_get_voltage(tdev->vdd);
|
||||
nvkm_info(&volt->base.subdev, "The default voltage is %duV\n", uv);
|
||||
|
||||
volt->vdd = device->gpu->vdd;
|
||||
volt->vdd = tdev->vdd;
|
||||
|
||||
volt->base.vid_nr = ARRAY_SIZE(gk20a_cvb_coef);
|
||||
nvkm_debug(&volt->base.subdev, "%s - vid_nr = %d\n", __func__,
|
||||
|
@ -180,7 +179,7 @@ gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
|
|||
volt->base.vid[i].vid = i;
|
||||
volt->base.vid[i].uv =
|
||||
gk20a_volt_calc_voltage(&gk20a_cvb_coef[i],
|
||||
device->gpu->gpu_speedo);
|
||||
tdev->gpu_speedo);
|
||||
nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i,
|
||||
volt->base.vid[i].vid, volt->base.vid[i].uv);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue