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staging: iio: meter: ade7854: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-08-07 16:12:17 +01:00
parent e48668a38b
commit 48a1319164
1 changed files with 1 additions and 1 deletions
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2
drivers/staging/iio/meter/ade7854.h
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@ -162,7 +162,7 @@ struct ade7854_state {
int bits);
int irq;
struct mutex buf_lock;
u8 tx[ADE7854_MAX_TX] ____cacheline_aligned;
u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN);
u8 rx[ADE7854_MAX_RX];
};