mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-04 09:59:32 +00:00
MIPS: Cleanup R10000_LLSC_WAR logic in atomic.h
This patch reduces down the conditionals in MIPS atomic code that deal
with a silicon bug in early R10000 cpus that required a workaround of
a branch-likely instruction following a store-conditional in order to
to guarantee the whole ll/sc sequence is atomic. As the only real
difference is a branch-likely instruction (beqzl) over a standard
branch (beqz), the conditional is reduced down to a single preprocessor
check at the top to pick the required instruction.
This requires writing the uses in assembler, thus we discard the
non-R10000 case that uses a mixture of a C do...while loop with
embedded assembler that was added back in commit 7837314d14
("MIPS:
Get rid of branches to .subsections."). A note found in the git log
for commit 5999eca25c1f ("[MIPS] Improve branch prediction in ll/sc
atomic operations.") is also addressed.
The macro definition for the branch instruction and the code comment
derives from a patch sent in earlier by Paul Burton for various cmpxchg
cleanups.
[paul.burton@mips.com:
- Minor whitespace fix for checkpatch.]
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/17736/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>
Cc: "Maciej W. Rozycki" <macro@mips.com>
Cc: linux-mips@linux-mips.org
This commit is contained in:
parent
a0a5ac3ce8
commit
4936084c2e
1 changed files with 32 additions and 147 deletions
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@ -22,6 +22,17 @@
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#include <asm/cmpxchg.h>
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#include <asm/war.h>
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/*
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* Using a branch-likely instruction to check the result of an sc instruction
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* works around a bug present in R10000 CPUs prior to revision 3.0 that could
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* cause ll-sc sequences to execute non-atomically.
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*/
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#if R10000_LLSC_WAR
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# define __scbeqz "beqzl"
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#else
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# define __scbeqz "beqz"
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#endif
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#define ATOMIC_INIT(i) { (i) }
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/*
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@ -44,31 +55,18 @@
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#define ATOMIC_OP(op, c_op, asm_op) \
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static __inline__ void atomic_##op(int i, atomic_t * v) \
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{ \
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %0, %1 # atomic_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" sc %0, %1 \n" \
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" beqzl %0, 1b \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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int temp; \
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\
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do { \
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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" ll %0, %1 # atomic_" #op "\n" \
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" " #asm_op " %0, %2 \n" \
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" sc %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!temp)); \
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} else { \
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unsigned long flags; \
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\
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@ -83,36 +81,20 @@ static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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{ \
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int result; \
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\
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_" #op "_return \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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" beqzl %0, 1b \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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int temp; \
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\
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do { \
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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" ll %1, %2 # atomic_" #op "_return \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!result)); \
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\
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result = temp; result c_op i; \
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} else { \
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unsigned long flags; \
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\
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@ -131,36 +113,20 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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{ \
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int result; \
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\
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_fetch_" #op " \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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" beqzl %0, 1b \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" move %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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int temp; \
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\
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do { \
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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" ll %1, %2 # atomic_fetch_" #op " \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!result)); \
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\
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result = temp; \
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} else { \
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unsigned long flags; \
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\
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@ -218,24 +184,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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int temp;
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__asm__ __volatile__(
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" .set arch=r4000 \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" subu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" sc %1, %2 \n"
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" beqzl %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
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: "memory");
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} else if (kernel_uses_llsc) {
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if (kernel_uses_llsc) {
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int temp;
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__asm__ __volatile__(
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@ -245,7 +194,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" sc %1, %2 \n"
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" beqz %1, 1b \n"
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"\t" __scbeqz " %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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@ -382,31 +331,18 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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#define ATOMIC64_OP(op, c_op, asm_op) \
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static __inline__ void atomic64_##op(long i, atomic64_t * v) \
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{ \
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %0, %1 # atomic64_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" scd %0, %1 \n" \
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" beqzl %0, 1b \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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long temp; \
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\
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do { \
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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" lld %0, %1 # atomic64_" #op "\n" \
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" " #asm_op " %0, %2 \n" \
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" scd %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} while (unlikely(!temp)); \
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} else { \
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unsigned long flags; \
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\
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@ -421,37 +357,20 @@ static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
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{ \
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long result; \
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\
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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" beqzl %0, 1b \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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long temp; \
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\
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do { \
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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" lld %1, %2 # atomic64_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"=" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
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: "memory"); \
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} while (unlikely(!result)); \
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\
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result = temp; result c_op i; \
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} else { \
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unsigned long flags; \
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\
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@ -474,33 +393,16 @@ static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set arch=r4000 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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" beqzl %0, 1b \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" move %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else if (kernel_uses_llsc) { \
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long temp; \
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\
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do { \
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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" lld %1, %2 # atomic64_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"=" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
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: "memory"); \
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} while (unlikely(!result)); \
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\
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result = temp; \
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} else { \
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unsigned long flags; \
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\
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@ -559,24 +461,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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long temp;
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__asm__ __volatile__(
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" .set arch=r4000 \n"
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"1: lld %1, %2 # atomic64_sub_if_positive\n"
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" dsubu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" scd %1, %2 \n"
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" beqzl %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"=" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
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: "memory");
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} else if (kernel_uses_llsc) {
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if (kernel_uses_llsc) {
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long temp;
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__asm__ __volatile__(
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" scd %1, %2 \n"
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" beqz %1, 1b \n"
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"\t" __scbeqz " %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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