mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
deca8322f1
commit
4ad5751a6c
1 changed files with 87 additions and 87 deletions
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@ -58,7 +58,7 @@ static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
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return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
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}
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/**
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@ -73,9 +73,9 @@ static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->uvd.ring_enc[0])
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR));
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return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
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else
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2));
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return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
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}
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/**
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@ -89,7 +89,7 @@ static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR));
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return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
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}
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/**
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@ -107,9 +107,9 @@ static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
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return adev->wb.wb[ring->wptr_offs];
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if (ring == &adev->uvd.ring_enc[0])
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR));
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return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
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else
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2));
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return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
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}
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/**
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@ -123,7 +123,7 @@ static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr));
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
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}
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/**
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@ -145,10 +145,10 @@ static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
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}
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if (ring == &adev->uvd.ring_enc[0])
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR),
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WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
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lower_32_bits(ring->wptr));
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else
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2),
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WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
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lower_32_bits(ring->wptr));
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}
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@ -617,46 +617,46 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
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uint32_t offset;
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
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offset = 0;
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} else {
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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lower_32_bits(adev->uvd.gpu_addr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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upper_32_bits(adev->uvd.gpu_addr));
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offset = size;
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}
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
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AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
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lower_32_bits(adev->uvd.gpu_addr + offset));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
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upper_32_bits(adev->uvd.gpu_addr + offset));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
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lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
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upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
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AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
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WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
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WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
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WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
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WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
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}
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static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
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@ -670,29 +670,29 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
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size = header->header_size + header->vce_table_size + header->uvd_table_size;
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/* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
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/* 2, update vmid of descriptor */
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data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
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data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
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data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
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data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
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/* 3, notify mmsch about the size of this descriptor */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
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/* 4, set resp to zero */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
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/* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
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data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
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data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
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loop = 1000;
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while ((data & 0x10000002) != 0x10000002) {
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udelay(10);
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data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
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data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
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loop--;
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if (!loop)
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break;
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@ -935,7 +935,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
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mdelay(1);
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/* put LMI, VCPU, RBC etc... into reset */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
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WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
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UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
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UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
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@ -947,7 +947,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
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mdelay(5);
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/* initialize UVD memory controller */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
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(0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
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UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
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UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
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@ -960,23 +960,23 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
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lmi_swap_cntl = 0xa;
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mp_swap_cntl = 0;
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#endif
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), lmi_swap_cntl);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), mp_swap_cntl);
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WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
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WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
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WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
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/* take all subblocks out of reset, except VCPU */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
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WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
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mdelay(5);
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/* enable VCPU clock */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
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WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
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UVD_VCPU_CNTL__CLK_EN_MASK);
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/* enable UMC */
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@ -984,14 +984,14 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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/* boot up the VCPU */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
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WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
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mdelay(10);
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for (i = 0; i < 10; ++i) {
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uint32_t status;
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for (j = 0; j < 100; ++j) {
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status = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS));
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status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
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if (status & 2)
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break;
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mdelay(10);
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@ -1032,44 +1032,44 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
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/* set the write pointer delay */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
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/* set the wb address */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
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(upper_32_bits(ring->gpu_addr) >> 2));
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/* programm the RB_BASE for ring buffer */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
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lower_32_bits(ring->gpu_addr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
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WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
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upper_32_bits(ring->gpu_addr));
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/* Initialize the ring buffer's read and write pointers */
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR), 0);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
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ring->wptr = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR),
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ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
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lower_32_bits(ring->wptr));
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
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~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
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ring = &adev->uvd.ring_enc[0];
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
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WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
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WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
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WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
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WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
|
||||
|
||||
ring = &adev->uvd.ring_enc[1];
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr));
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr));
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1084,7 +1084,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
|
|||
static void uvd_v7_0_stop(struct amdgpu_device *adev)
|
||||
{
|
||||
/* force RBC into idle state */
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0x11010101);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
|
||||
|
||||
/* Stall UMC and register bus before resetting VCPU */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
|
||||
|
@ -1093,12 +1093,12 @@ static void uvd_v7_0_stop(struct amdgpu_device *adev)
|
|||
mdelay(1);
|
||||
|
||||
/* put VCPU into reset */
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
|
||||
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
|
||||
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
|
||||
mdelay(5);
|
||||
|
||||
/* disable VCPU clock */
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0x0);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
|
||||
|
||||
/* Unstall UMC and register bus */
|
||||
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
|
||||
|
@ -1203,7 +1203,7 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
|
|||
unsigned i;
|
||||
int r;
|
||||
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
|
||||
r = amdgpu_ring_alloc(ring, 3);
|
||||
if (r) {
|
||||
DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
|
||||
|
@ -1215,7 +1215,7 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
|
|||
amdgpu_ring_write(ring, 0xDEADBEEF);
|
||||
amdgpu_ring_commit(ring);
|
||||
for (i = 0; i < adev->usec_timeout; i++) {
|
||||
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
|
||||
tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID);
|
||||
if (tmp == 0xDEADBEEF)
|
||||
break;
|
||||
DRM_UDELAY(1);
|
||||
|
@ -1413,8 +1413,8 @@ static bool uvd_v7_0_check_soft_reset(void *handle)
|
|||
|
||||
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
|
||||
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
|
||||
(RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS) &
|
||||
AMDGPU_UVD_STATUS_BUSY_MASK)))
|
||||
(RREG32_SOC15(UVD, 0, mmUVD_STATUS) &
|
||||
AMDGPU_UVD_STATUS_BUSY_MASK))
|
||||
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
|
||||
SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
|
||||
|
||||
|
@ -1521,9 +1521,9 @@ static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
|
|||
{
|
||||
uint32_t data, data1, data2, suvd_flags;
|
||||
|
||||
data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL));
|
||||
data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE));
|
||||
data2 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL));
|
||||
data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL);
|
||||
data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
|
||||
data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL);
|
||||
|
||||
data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
|
||||
UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
|
||||
|
@ -1567,18 +1567,18 @@ static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
|
|||
UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
|
||||
data1 |= suvd_flags;
|
||||
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), data);
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), 0);
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1);
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL), data2);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2);
|
||||
}
|
||||
|
||||
static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t data, data1, cgc_flags, suvd_flags;
|
||||
|
||||
data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE));
|
||||
data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE));
|
||||
data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE);
|
||||
data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
|
||||
|
||||
cgc_flags = UVD_CGC_GATE__SYS_MASK |
|
||||
UVD_CGC_GATE__UDEC_MASK |
|
||||
|
@ -1610,8 +1610,8 @@ static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
|
|||
data |= cgc_flags;
|
||||
data1 |= suvd_flags;
|
||||
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), data);
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
|
||||
}
|
||||
|
||||
static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
|
||||
|
@ -1670,7 +1670,7 @@ static int uvd_v7_0_set_powergating_state(void *handle,
|
|||
if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
|
||||
return 0;
|
||||
|
||||
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), UVD_POWER_STATUS__UVD_PG_EN_MASK);
|
||||
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
|
||||
|
||||
if (state == AMD_PG_STATE_GATE) {
|
||||
uvd_v7_0_stop(adev);
|
||||
|
|
Loading…
Reference in a new issue