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ARM: 8914/1: NOMMU: Fix exc_ret for XIP
It was reported that72cd4064fc
"NOMMU: Toggle only bits in EXC_RETURN we are really care of" breaks NOMMU+XIP combination. It happens because saved EXC_RETURN gets overwritten when data section is relocated. The fix is to propagate EXC_RETURN via register and let relocation code to commit that value into memory. Fixes:72cd4064fc
("ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care of") Reported-by: afzal mohammed <afzal.mohd.ma@gmail.com> Tested-by: afzal mohammed <afzal.mohd.ma@gmail.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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3 changed files with 7 additions and 5 deletions
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@ -68,7 +68,7 @@ ENDPROC(__vet_atags)
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* The following fragment of code is executed with the MMU on in MMU mode,
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* and uses absolute addresses; this is not position independent.
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*
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* r0 = cp#15 control register
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* r0 = cp#15 control register (exc_ret for M-class)
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* r1 = machine ID
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* r2 = atags/dtb pointer
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* r9 = processor ID
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@ -137,7 +137,8 @@ __mmap_switched_data:
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#ifdef CONFIG_CPU_CP15
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.long cr_alignment @ r3
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#else
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.long 0 @ r3
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M_CLASS(.long exc_ret) @ r3
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AR_CLASS(.long 0) @ r3
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#endif
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.size __mmap_switched_data, . - __mmap_switched_data
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@ -201,6 +201,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1])
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bic r0, r0, #V7M_SCB_CCR_IC
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#endif
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str r0, [r12, V7M_SCB_CCR]
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/* Pass exc_ret to __mmap_switched */
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mov r0, r10
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#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
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ret lr
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ENDPROC(__after_proc_init)
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@ -136,9 +136,8 @@ __v7m_setup_cont:
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cpsie i
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svc #0
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1: cpsid i
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ldr r0, =exc_ret
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orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
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str lr, [r0]
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/* Calculate exc_ret */
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orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
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ldmia sp, {r0-r3, r12}
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str r5, [r12, #11 * 4] @ restore the original SVC vector entry
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mov lr, r6 @ restore LR
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