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sh-pfc: r8a73a4: Add IRQC pin groups and functions
V2 of PINCTRL support for r8a73a4 IRQC hardware and in particular the external pins IRQ0 -> IRQ57. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Magnus Damm
Simon Horman
parent
172fd616dd
commit
515a828f77
1 changed files with 186 additions and 0 deletions
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@ -1576,6 +1576,72 @@ static const struct pinmux_range pinmux_ranges[] = {
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{.begin = 320, .end = 329,},
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};
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/* - IRQC ------------------------------------------------------------------- */
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#define IRQC_PINS_MUX(pin, irq_mark) \
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static const unsigned int irqc_irq##irq_mark##_pins[] = { \
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pin, \
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}; \
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static const unsigned int irqc_irq##irq_mark##_mux[] = { \
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IRQ##irq_mark##_MARK, \
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}
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IRQC_PINS_MUX(0, 0);
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IRQC_PINS_MUX(1, 1);
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IRQC_PINS_MUX(2, 2);
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IRQC_PINS_MUX(3, 3);
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IRQC_PINS_MUX(4, 4);
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IRQC_PINS_MUX(5, 5);
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IRQC_PINS_MUX(6, 6);
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IRQC_PINS_MUX(7, 7);
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IRQC_PINS_MUX(8, 8);
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IRQC_PINS_MUX(9, 9);
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IRQC_PINS_MUX(10, 10);
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IRQC_PINS_MUX(11, 11);
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IRQC_PINS_MUX(12, 12);
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IRQC_PINS_MUX(13, 13);
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IRQC_PINS_MUX(14, 14);
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IRQC_PINS_MUX(15, 15);
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IRQC_PINS_MUX(66, 40);
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IRQC_PINS_MUX(84, 19);
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IRQC_PINS_MUX(85, 18);
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IRQC_PINS_MUX(102, 41);
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IRQC_PINS_MUX(103, 42);
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IRQC_PINS_MUX(109, 43);
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IRQC_PINS_MUX(110, 44);
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IRQC_PINS_MUX(111, 45);
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IRQC_PINS_MUX(112, 46);
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IRQC_PINS_MUX(113, 47);
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IRQC_PINS_MUX(114, 48);
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IRQC_PINS_MUX(115, 49);
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IRQC_PINS_MUX(160, 20);
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IRQC_PINS_MUX(161, 21);
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IRQC_PINS_MUX(162, 22);
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IRQC_PINS_MUX(163, 23);
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IRQC_PINS_MUX(175, 24);
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IRQC_PINS_MUX(176, 25);
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IRQC_PINS_MUX(177, 26);
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IRQC_PINS_MUX(178, 27);
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IRQC_PINS_MUX(192, 31);
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IRQC_PINS_MUX(193, 32);
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IRQC_PINS_MUX(194, 33);
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IRQC_PINS_MUX(195, 34);
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IRQC_PINS_MUX(196, 35);
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IRQC_PINS_MUX(197, 36);
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IRQC_PINS_MUX(198, 37);
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IRQC_PINS_MUX(199, 38);
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IRQC_PINS_MUX(200, 39);
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IRQC_PINS_MUX(290, 51);
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IRQC_PINS_MUX(296, 52);
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IRQC_PINS_MUX(301, 50);
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IRQC_PINS_MUX(320, 16);
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IRQC_PINS_MUX(321, 17);
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IRQC_PINS_MUX(322, 28);
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IRQC_PINS_MUX(323, 29);
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IRQC_PINS_MUX(324, 30);
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IRQC_PINS_MUX(325, 53);
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IRQC_PINS_MUX(326, 54);
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IRQC_PINS_MUX(327, 55);
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IRQC_PINS_MUX(328, 56);
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IRQC_PINS_MUX(329, 57);
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/* - SCIFA0 ----------------------------------------------------------------- */
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static const unsigned int scifa0_data_pins[] = {
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/* SCIFA0_RXD, SCIFA0_TXD */
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@ -1773,6 +1839,64 @@ static const unsigned int scifb3_ctrl_b_mux[] = {
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(irqc_irq0),
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SH_PFC_PIN_GROUP(irqc_irq1),
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SH_PFC_PIN_GROUP(irqc_irq2),
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SH_PFC_PIN_GROUP(irqc_irq3),
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SH_PFC_PIN_GROUP(irqc_irq4),
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SH_PFC_PIN_GROUP(irqc_irq5),
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SH_PFC_PIN_GROUP(irqc_irq6),
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SH_PFC_PIN_GROUP(irqc_irq7),
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SH_PFC_PIN_GROUP(irqc_irq8),
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SH_PFC_PIN_GROUP(irqc_irq9),
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SH_PFC_PIN_GROUP(irqc_irq10),
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SH_PFC_PIN_GROUP(irqc_irq11),
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SH_PFC_PIN_GROUP(irqc_irq12),
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SH_PFC_PIN_GROUP(irqc_irq13),
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SH_PFC_PIN_GROUP(irqc_irq14),
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SH_PFC_PIN_GROUP(irqc_irq15),
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SH_PFC_PIN_GROUP(irqc_irq16),
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SH_PFC_PIN_GROUP(irqc_irq17),
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SH_PFC_PIN_GROUP(irqc_irq18),
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SH_PFC_PIN_GROUP(irqc_irq19),
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SH_PFC_PIN_GROUP(irqc_irq20),
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SH_PFC_PIN_GROUP(irqc_irq21),
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SH_PFC_PIN_GROUP(irqc_irq22),
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SH_PFC_PIN_GROUP(irqc_irq23),
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SH_PFC_PIN_GROUP(irqc_irq24),
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SH_PFC_PIN_GROUP(irqc_irq25),
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SH_PFC_PIN_GROUP(irqc_irq26),
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SH_PFC_PIN_GROUP(irqc_irq27),
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SH_PFC_PIN_GROUP(irqc_irq28),
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SH_PFC_PIN_GROUP(irqc_irq29),
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SH_PFC_PIN_GROUP(irqc_irq30),
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SH_PFC_PIN_GROUP(irqc_irq31),
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SH_PFC_PIN_GROUP(irqc_irq32),
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SH_PFC_PIN_GROUP(irqc_irq33),
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SH_PFC_PIN_GROUP(irqc_irq34),
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SH_PFC_PIN_GROUP(irqc_irq35),
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SH_PFC_PIN_GROUP(irqc_irq36),
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SH_PFC_PIN_GROUP(irqc_irq37),
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SH_PFC_PIN_GROUP(irqc_irq38),
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SH_PFC_PIN_GROUP(irqc_irq39),
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SH_PFC_PIN_GROUP(irqc_irq40),
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SH_PFC_PIN_GROUP(irqc_irq41),
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SH_PFC_PIN_GROUP(irqc_irq42),
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SH_PFC_PIN_GROUP(irqc_irq43),
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SH_PFC_PIN_GROUP(irqc_irq44),
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SH_PFC_PIN_GROUP(irqc_irq45),
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SH_PFC_PIN_GROUP(irqc_irq46),
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SH_PFC_PIN_GROUP(irqc_irq47),
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SH_PFC_PIN_GROUP(irqc_irq48),
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SH_PFC_PIN_GROUP(irqc_irq49),
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SH_PFC_PIN_GROUP(irqc_irq50),
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SH_PFC_PIN_GROUP(irqc_irq51),
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SH_PFC_PIN_GROUP(irqc_irq52),
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SH_PFC_PIN_GROUP(irqc_irq53),
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SH_PFC_PIN_GROUP(irqc_irq54),
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SH_PFC_PIN_GROUP(irqc_irq55),
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SH_PFC_PIN_GROUP(irqc_irq56),
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SH_PFC_PIN_GROUP(irqc_irq57),
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SH_PFC_PIN_GROUP(scifa0_data),
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SH_PFC_PIN_GROUP(scifa0_clk),
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SH_PFC_PIN_GROUP(scifa0_ctrl),
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@ -1802,6 +1926,67 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scifb3_ctrl_b),
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};
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static const char * const irqc_groups[] = {
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"irqc_irq0",
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"irqc_irq1",
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"irqc_irq2",
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"irqc_irq3",
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"irqc_irq4",
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"irqc_irq5",
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"irqc_irq6",
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"irqc_irq7",
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"irqc_irq8",
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"irqc_irq9",
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"irqc_irq10",
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"irqc_irq11",
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"irqc_irq12",
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"irqc_irq13",
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"irqc_irq14",
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"irqc_irq15",
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"irqc_irq16",
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"irqc_irq17",
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"irqc_irq18",
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"irqc_irq19",
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"irqc_irq20",
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"irqc_irq21",
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"irqc_irq22",
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"irqc_irq23",
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"irqc_irq24",
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"irqc_irq25",
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"irqc_irq26",
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"irqc_irq27",
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"irqc_irq28",
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"irqc_irq29",
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"irqc_irq30",
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"irqc_irq31",
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"irqc_irq32",
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"irqc_irq33",
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"irqc_irq34",
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"irqc_irq35",
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"irqc_irq36",
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"irqc_irq37",
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"irqc_irq38",
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"irqc_irq39",
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"irqc_irq40",
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"irqc_irq41",
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"irqc_irq42",
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"irqc_irq43",
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"irqc_irq44",
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"irqc_irq45",
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"irqc_irq46",
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"irqc_irq47",
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"irqc_irq48",
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"irqc_irq49",
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"irqc_irq50",
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"irqc_irq51",
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"irqc_irq52",
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"irqc_irq53",
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"irqc_irq54",
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"irqc_irq55",
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"irqc_irq56",
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"irqc_irq57",
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};
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static const char * const scifa0_groups[] = {
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"scifa0_data",
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"scifa0_clk",
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@ -1848,6 +2033,7 @@ static const char * const scifb3_groups[] = {
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};
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(irqc),
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SH_PFC_FUNCTION(scifa0),
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SH_PFC_FUNCTION(scifa1),
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SH_PFC_FUNCTION(scifb0),
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