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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
drm/amdgpu: add interface for editing a foreign process's priority v3
The AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE ioctls are used to set the priority of a different process in the current system. When a request is dropped, the process's contexts will be restored to the priority specified at context creation time. A request can be dropped by setting the override priority to AMDGPU_CTX_PRIORITY_UNSET. An fd is used to identify the remote process. This is simpler than passing a pid number, which is vulnerable to re-use, etc. This functionality is limited to DRM_MASTER since abuse of this interface can have a negative impact on the system's performance. v2: removed unused output structure v3: change refcounted interface for a regular set operation Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
c23be4ae1d
commit
52c6a62c64
6 changed files with 164 additions and 21 deletions
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@ -25,7 +25,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
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amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
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amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
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amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
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amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
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amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
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amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
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amdgpu_queue_mgr.o amdgpu_vf_error.o
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amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o
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# add asic specific block
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# add asic specific block
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amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
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amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
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@ -25,6 +25,7 @@
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#include <drm/drmP.h>
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#include <drm/drmP.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_auth.h>
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#include "amdgpu.h"
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#include "amdgpu.h"
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#include "amdgpu_sched.h"
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static int amdgpu_ctx_priority_permit(struct drm_file *filp,
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static int amdgpu_ctx_priority_permit(struct drm_file *filp,
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enum amd_sched_priority priority)
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enum amd_sched_priority priority)
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@ -220,26 +221,6 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
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return 0;
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return 0;
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}
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}
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static enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
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{
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switch (amdgpu_priority) {
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case AMDGPU_CTX_PRIORITY_HIGH_HW:
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return AMD_SCHED_PRIORITY_HIGH_HW;
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case AMDGPU_CTX_PRIORITY_HIGH_SW:
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return AMD_SCHED_PRIORITY_HIGH_SW;
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case AMDGPU_CTX_PRIORITY_NORMAL:
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return AMD_SCHED_PRIORITY_NORMAL;
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case AMDGPU_CTX_PRIORITY_LOW_SW:
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case AMDGPU_CTX_PRIORITY_LOW_HW:
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return AMD_SCHED_PRIORITY_LOW;
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case AMDGPU_CTX_PRIORITY_UNSET:
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return AMD_SCHED_PRIORITY_UNSET;
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default:
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WARN(1, "Invalid context priority %d\n", amdgpu_priority);
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return AMD_SCHED_PRIORITY_INVALID;
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}
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}
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int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
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int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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struct drm_file *filp)
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{
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{
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@ -28,6 +28,7 @@
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#include <drm/drmP.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu.h"
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#include <drm/amdgpu_drm.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu_sched.h"
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#include "amdgpu_uvd.h"
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#include "amdgpu_uvd.h"
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#include "amdgpu_vce.h"
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#include "amdgpu_vce.h"
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@ -1023,6 +1024,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
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DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
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DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
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/* KMS */
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/* KMS */
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109
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
Normal file
109
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
Normal file
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@ -0,0 +1,109 @@
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/*
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* Copyright 2017 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Andres Rodriguez <andresx7@gmail.com>
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*/
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#include <linux/fdtable.h>
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#include <linux/pid.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_vm.h"
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enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
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{
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switch (amdgpu_priority) {
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case AMDGPU_CTX_PRIORITY_HIGH_HW:
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return AMD_SCHED_PRIORITY_HIGH_HW;
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case AMDGPU_CTX_PRIORITY_HIGH_SW:
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return AMD_SCHED_PRIORITY_HIGH_SW;
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case AMDGPU_CTX_PRIORITY_NORMAL:
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return AMD_SCHED_PRIORITY_NORMAL;
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case AMDGPU_CTX_PRIORITY_LOW_SW:
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case AMDGPU_CTX_PRIORITY_LOW_HW:
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return AMD_SCHED_PRIORITY_LOW;
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case AMDGPU_CTX_PRIORITY_UNSET:
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return AMD_SCHED_PRIORITY_UNSET;
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default:
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WARN(1, "Invalid context priority %d\n", amdgpu_priority);
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return AMD_SCHED_PRIORITY_INVALID;
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}
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}
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static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
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int fd,
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enum amd_sched_priority priority)
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{
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struct file *filp = fcheck(fd);
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struct drm_file *file;
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struct pid *pid;
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struct amdgpu_fpriv *fpriv;
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struct amdgpu_ctx *ctx;
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uint32_t id;
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if (!filp)
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return -EINVAL;
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pid = get_pid(((struct drm_file *)filp->private_data)->pid);
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mutex_lock(&adev->ddev->filelist_mutex);
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list_for_each_entry(file, &adev->ddev->filelist, lhead) {
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if (file->pid != pid)
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continue;
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fpriv = file->driver_priv;
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idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
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amdgpu_ctx_priority_override(ctx, priority);
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}
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mutex_unlock(&adev->ddev->filelist_mutex);
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put_pid(pid);
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return 0;
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}
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int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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union drm_amdgpu_sched *args = data;
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struct amdgpu_device *adev = dev->dev_private;
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enum amd_sched_priority priority;
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int r;
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priority = amdgpu_to_sched_priority(args->in.priority);
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if (args->in.flags || priority == AMD_SCHED_PRIORITY_INVALID)
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return -EINVAL;
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switch (args->in.op) {
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case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
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r = amdgpu_sched_process_priority_override(adev,
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args->in.fd,
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priority);
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break;
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default:
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DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
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r = -EINVAL;
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break;
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}
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return r;
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}
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34
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
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34
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
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@ -0,0 +1,34 @@
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/*
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* Copyright 2017 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Andres Rodriguez <andresx7@gmail.com>
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*/
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#ifndef __AMDGPU_SCHED_H__
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#define __AMDGPU_SCHED_H__
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#include <drm/drmP.h>
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enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority);
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int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp);
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#endif // __AMDGPU_SCHED_H__
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@ -53,6 +53,7 @@ extern "C" {
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#define DRM_AMDGPU_WAIT_FENCES 0x12
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#define DRM_AMDGPU_WAIT_FENCES 0x12
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#define DRM_AMDGPU_VM 0x13
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#define DRM_AMDGPU_VM 0x13
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#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
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#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
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#define DRM_AMDGPU_SCHED 0x15
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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@ -69,6 +70,7 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
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#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
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#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
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#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
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#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
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#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
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#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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struct drm_amdgpu_vm_out out;
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struct drm_amdgpu_vm_out out;
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};
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};
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/* sched ioctl */
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#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
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struct drm_amdgpu_sched_in {
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/* AMDGPU_SCHED_OP_* */
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__u32 op;
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__u32 fd;
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__s32 priority;
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__u32 flags;
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};
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union drm_amdgpu_sched {
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struct drm_amdgpu_sched_in in;
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};
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/*
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/*
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* This is not a reliable API and you should expect it to fail for any
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* This is not a reliable API and you should expect it to fail for any
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* number of reasons and have fallback path that do not use userptr to
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* number of reasons and have fallback path that do not use userptr to
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