mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge tag 'drm-intel-fixes-2021-02-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.11-rc7: - Skip vswing programming for TBT - Power up combo PHY lanes for HDMI - Fix double YUV range correction on HDR planes - Fix the MST PBN divider calculation - Fix LTTPR vswing/pre-emp setting in non-transparent mode - Move the breadcrumb to the signaler if completed upon cancel - Close race between enable_breadcrumbs and cancel_breadcrumbs - Drop lru bumping on display unpinning Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87bld0f36b.fsf@intel.com
This commit is contained in:
commit
59854811c0
14 changed files with 119 additions and 177 deletions
|
@ -3629,14 +3629,26 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
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return 0;
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}
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static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8 dp_link_count)
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/**
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* drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
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* @link_rate: link rate in 10kbits/s units
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* @link_lane_count: lane count
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*
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* Calculate the total bandwidth of a MultiStream Transport link. The returned
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* value is in units of PBNs/(timeslots/1 MTP). This value can be used to
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* convert the number of PBNs required for a given stream to the number of
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* timeslots this stream requires in each MTP.
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*/
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int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
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{
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if (dp_link_bw == 0 || dp_link_count == 0)
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DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",
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dp_link_bw, dp_link_count);
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if (link_rate == 0 || link_lane_count == 0)
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DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
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link_rate, link_lane_count);
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return dp_link_bw * dp_link_count / 2;
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/* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
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return link_rate * link_lane_count / 54000;
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}
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EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
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/**
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* drm_dp_read_mst_cap() - check whether or not a sink supports MST
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@ -3692,7 +3704,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
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goto out_unlock;
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}
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mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1],
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mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
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mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK);
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if (mgr->pbn_div == 0) {
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ret = -EINVAL;
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@ -2754,6 +2754,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
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int n_entries, ln;
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u32 val;
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if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
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return;
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ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
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if (level >= n_entries) {
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drm_dbg_kms(&dev_priv->drm,
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@ -2890,6 +2893,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
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u32 val, dpcnt_mask, dpcnt_val;
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int n_entries, ln;
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if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
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return;
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ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
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if (level >= n_entries)
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@ -3531,6 +3537,23 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
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intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
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}
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static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
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enum phy phy = intel_port_to_phy(i915, encoder->port);
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if (intel_phy_is_combo(i915, phy)) {
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bool lane_reversal =
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dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
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intel_combo_phy_power_up_lanes(i915, phy, false,
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crtc_state->lane_count,
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lane_reversal);
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}
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}
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static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
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struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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@ -3620,14 +3643,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
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* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
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* the used lanes of the DDI.
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*/
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if (intel_phy_is_combo(dev_priv, phy)) {
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bool lane_reversal =
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dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
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intel_combo_phy_power_up_lanes(dev_priv, phy, false,
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crtc_state->lane_count,
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lane_reversal);
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}
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intel_ddi_power_up_lanes(encoder, crtc_state);
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/*
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* 7.g Configure and enable DDI_BUF_CTL
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@ -3712,14 +3728,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
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else
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intel_prepare_dp_ddi_buffers(encoder, crtc_state);
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if (intel_phy_is_combo(dev_priv, phy)) {
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bool lane_reversal =
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dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
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intel_combo_phy_power_up_lanes(dev_priv, phy, false,
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crtc_state->lane_count,
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lane_reversal);
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}
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intel_ddi_power_up_lanes(encoder, crtc_state);
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intel_ddi_init_dp_buf_reg(encoder, crtc_state);
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if (!is_mst)
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@ -4205,6 +4214,8 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
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intel_de_write(dev_priv, reg, val);
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}
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intel_ddi_power_up_lanes(encoder, crtc_state);
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/* In HDMI/DVI mode, the port width, and swing/emphasis values
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* are ignored so nothing special needs to be done besides
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* enabling the port.
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@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
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*/
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ret = i915_vma_pin_fence(vma);
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if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
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i915_gem_object_unpin_from_display_plane(vma);
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i915_vma_unpin(vma);
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vma = ERR_PTR(ret);
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goto err;
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}
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@ -2327,12 +2327,9 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
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void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
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{
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i915_gem_object_lock(vma->obj, NULL);
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if (flags & PLANE_HAS_FENCE)
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i915_vma_unpin_fence(vma);
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i915_gem_object_unpin_from_display_plane(vma);
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i915_gem_object_unlock(vma->obj);
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i915_vma_unpin(vma);
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i915_vma_put(vma);
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}
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@ -4807,6 +4804,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
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plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
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} else if (fb->format->is_yuv) {
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plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
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if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
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plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
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}
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return plane_color_ctl;
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@ -4637,24 +4637,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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}
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void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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u8 train_set = intel_dp->train_set[0];
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drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
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train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
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train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
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drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
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(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
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DP_TRAIN_PRE_EMPHASIS_SHIFT,
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train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
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" (max)" : "");
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intel_dp->set_signal_levels(intel_dp, crtc_state);
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}
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void
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intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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@ -5703,7 +5685,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
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intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
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intel_dp_set_signal_levels(intel_dp, crtc_state);
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intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
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intel_dp_phy_pattern_update(intel_dp, crtc_state);
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|
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@ -96,9 +96,6 @@ void
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intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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u8 dp_train_pat);
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void
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intel_dp_set_signal_levels(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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u8 *link_bw, u8 *rate_select);
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bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
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|
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@ -334,6 +334,27 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
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return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
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}
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void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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u8 train_set = intel_dp->train_set[0];
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char phy_name[10];
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drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
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train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
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train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
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(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
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DP_TRAIN_PRE_EMPHASIS_SHIFT,
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train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
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" (max)" : "",
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intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
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|
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if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
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intel_dp->set_signal_levels(intel_dp, crtc_state);
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}
|
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|
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static bool
|
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intel_dp_reset_link_train(struct intel_dp *intel_dp,
|
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const struct intel_crtc_state *crtc_state,
|
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|
@ -341,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
|
|||
u8 dp_train_pat)
|
||||
{
|
||||
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
|
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intel_dp_set_signal_levels(intel_dp, crtc_state);
|
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intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
|
||||
return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
|
||||
}
|
||||
|
||||
|
@ -355,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
|
|||
DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
|
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int ret;
|
||||
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state);
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
|
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|
||||
ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
|
||||
intel_dp->train_set, crtc_state->lane_count);
|
||||
|
|
|
@ -17,6 +17,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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|||
const struct intel_crtc_state *crtc_state,
|
||||
enum drm_dp_phy dp_phy,
|
||||
const u8 link_status[DP_LINK_STATUS_SIZE]);
|
||||
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
enum drm_dp_phy dp_phy);
|
||||
void intel_dp_start_link_train(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state);
|
||||
void intel_dp_stop_link_train(struct intel_dp *intel_dp,
|
||||
|
|
|
@ -69,7 +69,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
|
|||
|
||||
slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
|
||||
connector->port,
|
||||
crtc_state->pbn, 0);
|
||||
crtc_state->pbn,
|
||||
drm_dp_get_vc_payload_bw(crtc_state->port_clock,
|
||||
crtc_state->lane_count));
|
||||
if (slots == -EDEADLK)
|
||||
return slots;
|
||||
if (slots >= 0)
|
||||
|
|
|
@ -359,7 +359,7 @@ static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
|
|||
intel_frontbuffer_flip_complete(overlay->i915,
|
||||
INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
|
||||
|
||||
i915_gem_object_unpin_from_display_plane(vma);
|
||||
i915_vma_unpin(vma);
|
||||
i915_vma_put(vma);
|
||||
}
|
||||
|
||||
|
@ -860,7 +860,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
|
|||
return 0;
|
||||
|
||||
out_unpin:
|
||||
i915_gem_object_unpin_from_display_plane(vma);
|
||||
i915_vma_unpin(vma);
|
||||
out_pin_section:
|
||||
atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
|
||||
|
||||
|
|
|
@ -618,13 +618,19 @@ skl_program_scaler(struct intel_plane *plane,
|
|||
|
||||
/* Preoffset values for YUV to RGB Conversion */
|
||||
#define PREOFF_YUV_TO_RGB_HI 0x1800
|
||||
#define PREOFF_YUV_TO_RGB_ME 0x1F00
|
||||
#define PREOFF_YUV_TO_RGB_ME 0x0000
|
||||
#define PREOFF_YUV_TO_RGB_LO 0x1800
|
||||
|
||||
#define ROFF(x) (((x) & 0xffff) << 16)
|
||||
#define GOFF(x) (((x) & 0xffff) << 0)
|
||||
#define BOFF(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/*
|
||||
* Programs the input color space conversion stage for ICL HDR planes.
|
||||
* Note that it is assumed that this stage always happens after YUV
|
||||
* range correction. Thus, the input to this stage is assumed to be
|
||||
* in full-range YCbCr.
|
||||
*/
|
||||
static void
|
||||
icl_program_input_csc(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
@ -672,52 +678,7 @@ icl_program_input_csc(struct intel_plane *plane,
|
|||
0x0, 0x7800, 0x7F10,
|
||||
},
|
||||
};
|
||||
|
||||
/* Matrix for Limited Range to Full Range Conversion */
|
||||
static const u16 input_csc_matrix_lr[][9] = {
|
||||
/*
|
||||
* BT.601 Limted range YCbCr -> full range RGB
|
||||
* The matrix required is :
|
||||
* [1.164384, 0.000, 1.596027,
|
||||
* 1.164384, -0.39175, -0.812813,
|
||||
* 1.164384, 2.017232, 0.0000]
|
||||
*/
|
||||
[DRM_COLOR_YCBCR_BT601] = {
|
||||
0x7CC8, 0x7950, 0x0,
|
||||
0x8D00, 0x7950, 0x9C88,
|
||||
0x0, 0x7950, 0x6810,
|
||||
},
|
||||
/*
|
||||
* BT.709 Limited range YCbCr -> full range RGB
|
||||
* The matrix required is :
|
||||
* [1.164384, 0.000, 1.792741,
|
||||
* 1.164384, -0.213249, -0.532909,
|
||||
* 1.164384, 2.112402, 0.0000]
|
||||
*/
|
||||
[DRM_COLOR_YCBCR_BT709] = {
|
||||
0x7E58, 0x7950, 0x0,
|
||||
0x8888, 0x7950, 0xADA8,
|
||||
0x0, 0x7950, 0x6870,
|
||||
},
|
||||
/*
|
||||
* BT.2020 Limited range YCbCr -> full range RGB
|
||||
* The matrix required is :
|
||||
* [1.164, 0.000, 1.678,
|
||||
* 1.164, -0.1873, -0.6504,
|
||||
* 1.164, 2.1417, 0.0000]
|
||||
*/
|
||||
[DRM_COLOR_YCBCR_BT2020] = {
|
||||
0x7D70, 0x7950, 0x0,
|
||||
0x8A68, 0x7950, 0xAC00,
|
||||
0x0, 0x7950, 0x6890,
|
||||
},
|
||||
};
|
||||
const u16 *csc;
|
||||
|
||||
if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
|
||||
csc = input_csc_matrix[plane_state->hw.color_encoding];
|
||||
else
|
||||
csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
|
||||
const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
|
||||
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
|
||||
ROFF(csc[0]) | GOFF(csc[1]));
|
||||
|
@ -734,14 +695,8 @@ icl_program_input_csc(struct intel_plane *plane,
|
|||
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
|
||||
PREOFF_YUV_TO_RGB_HI);
|
||||
if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
|
||||
intel_de_write_fw(dev_priv,
|
||||
PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
|
||||
0);
|
||||
else
|
||||
intel_de_write_fw(dev_priv,
|
||||
PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
|
||||
PREOFF_YUV_TO_RGB_ME);
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
|
||||
PREOFF_YUV_TO_RGB_ME);
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
|
||||
PREOFF_YUV_TO_RGB_LO);
|
||||
intel_de_write_fw(dev_priv,
|
||||
|
|
|
@ -387,48 +387,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
|
|||
return vma;
|
||||
}
|
||||
|
||||
static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(obj->base.dev);
|
||||
struct i915_vma *vma;
|
||||
|
||||
if (list_empty(&obj->vma.list))
|
||||
return;
|
||||
|
||||
mutex_lock(&i915->ggtt.vm.mutex);
|
||||
spin_lock(&obj->vma.lock);
|
||||
for_each_ggtt_vma(vma, obj) {
|
||||
if (!drm_mm_node_allocated(&vma->node))
|
||||
continue;
|
||||
|
||||
GEM_BUG_ON(vma->vm != &i915->ggtt.vm);
|
||||
list_move_tail(&vma->vm_link, &vma->vm->bound_list);
|
||||
}
|
||||
spin_unlock(&obj->vma.lock);
|
||||
mutex_unlock(&i915->ggtt.vm.mutex);
|
||||
|
||||
if (i915_gem_object_is_shrinkable(obj)) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i915->mm.obj_lock, flags);
|
||||
|
||||
if (obj->mm.madv == I915_MADV_WILLNEED &&
|
||||
!atomic_read(&obj->mm.shrink_pin))
|
||||
list_move_tail(&obj->mm.link, &i915->mm.shrink_list);
|
||||
|
||||
spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
|
||||
{
|
||||
/* Bump the LRU to try and avoid premature eviction whilst flipping */
|
||||
i915_gem_object_bump_inactive_ggtt(vma->obj);
|
||||
|
||||
i915_vma_unpin(vma);
|
||||
}
|
||||
|
||||
/**
|
||||
* Moves a single object to the CPU read, and possibly write domain.
|
||||
* @obj: object to act on
|
||||
|
@ -569,9 +527,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
|
|||
else
|
||||
err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
|
||||
|
||||
/* And bump the LRU for this access */
|
||||
i915_gem_object_bump_inactive_ggtt(obj);
|
||||
|
||||
i915_gem_object_unlock(obj);
|
||||
|
||||
if (write_domain)
|
||||
|
|
|
@ -486,7 +486,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
|
|||
u32 alignment,
|
||||
const struct i915_ggtt_view *view,
|
||||
unsigned int flags);
|
||||
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
|
||||
|
||||
void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj);
|
||||
void i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj);
|
||||
|
|
|
@ -187,18 +187,6 @@ static void add_retire(struct intel_breadcrumbs *b, struct intel_timeline *tl)
|
|||
intel_engine_add_retire(b->irq_engine, tl);
|
||||
}
|
||||
|
||||
static bool __signal_request(struct i915_request *rq)
|
||||
{
|
||||
GEM_BUG_ON(test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags));
|
||||
|
||||
if (!__dma_fence_signal(&rq->fence)) {
|
||||
i915_request_put(rq);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct llist_node *
|
||||
slist_add(struct llist_node *node, struct llist_node *head)
|
||||
{
|
||||
|
@ -269,9 +257,11 @@ static void signal_irq_work(struct irq_work *work)
|
|||
release = remove_signaling_context(b, ce);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
|
||||
if (__signal_request(rq))
|
||||
if (__dma_fence_signal(&rq->fence))
|
||||
/* We own signal_node now, xfer to local list */
|
||||
signal = slist_add(&rq->signal_node, signal);
|
||||
else
|
||||
i915_request_put(rq);
|
||||
|
||||
if (release) {
|
||||
add_retire(b, ce->timeline);
|
||||
|
@ -358,6 +348,17 @@ void intel_breadcrumbs_free(struct intel_breadcrumbs *b)
|
|||
kfree(b);
|
||||
}
|
||||
|
||||
static void irq_signal_request(struct i915_request *rq,
|
||||
struct intel_breadcrumbs *b)
|
||||
{
|
||||
if (!__dma_fence_signal(&rq->fence))
|
||||
return;
|
||||
|
||||
i915_request_get(rq);
|
||||
if (llist_add(&rq->signal_node, &b->signaled_requests))
|
||||
irq_work_queue(&b->irq_work);
|
||||
}
|
||||
|
||||
static void insert_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
|
@ -367,17 +368,13 @@ static void insert_breadcrumb(struct i915_request *rq)
|
|||
if (test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
|
||||
return;
|
||||
|
||||
i915_request_get(rq);
|
||||
|
||||
/*
|
||||
* If the request is already completed, we can transfer it
|
||||
* straight onto a signaled list, and queue the irq worker for
|
||||
* its signal completion.
|
||||
*/
|
||||
if (__i915_request_is_complete(rq)) {
|
||||
if (__signal_request(rq) &&
|
||||
llist_add(&rq->signal_node, &b->signaled_requests))
|
||||
irq_work_queue(&b->irq_work);
|
||||
irq_signal_request(rq, b);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -408,6 +405,8 @@ static void insert_breadcrumb(struct i915_request *rq)
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
i915_request_get(rq);
|
||||
list_add_rcu(&rq->signal_link, pos);
|
||||
GEM_BUG_ON(!check_signal_order(ce, rq));
|
||||
GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
|
||||
|
@ -448,19 +447,25 @@ bool i915_request_enable_breadcrumb(struct i915_request *rq)
|
|||
|
||||
void i915_request_cancel_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
struct intel_context *ce = rq->context;
|
||||
bool release;
|
||||
|
||||
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
|
||||
return;
|
||||
|
||||
spin_lock(&ce->signal_lock);
|
||||
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) {
|
||||
spin_unlock(&ce->signal_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
list_del_rcu(&rq->signal_link);
|
||||
release = remove_signaling_context(rq->engine->breadcrumbs, ce);
|
||||
release = remove_signaling_context(b, ce);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
if (release)
|
||||
intel_context_put(ce);
|
||||
|
||||
if (__i915_request_is_complete(rq))
|
||||
irq_signal_request(rq, b);
|
||||
|
||||
i915_request_put(rq);
|
||||
}
|
||||
|
||||
|
|
|
@ -783,6 +783,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
|
|||
|
||||
struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
|
||||
|
||||
int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
|
||||
|
||||
int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
|
||||
|
||||
|
|
Loading…
Reference in a new issue