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arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
commitde60edf1be
upstream. Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org Fixes:8abae9389b
("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 5 additions and 1 deletions
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@ -59,7 +59,10 @@ gic500: interrupt-controller@1800000 {
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#interrupt-cells = <3>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01840000 0x00 0xC0000>; /* GICR */
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<0x00 0x01840000 0x00 0xC0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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/*
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/*
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* vcpumntirq:
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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* virtual CPU interface maintenance interrupt
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@ -85,6 +85,7 @@ cbass_main: bus@f4000 {
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<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
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<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
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<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
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<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
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<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
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