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drm/amdgpu/vpe: enable vpe dpm
enable vpe dpm Signed-off-by: Peyton Lee <peytolee@amd.com> Reviewed-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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b8b92c1bd7
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5f82a0c90c
3 changed files with 276 additions and 0 deletions
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@ -26,6 +26,7 @@
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#include "amdgpu.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_vpe.h"
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#include "amdgpu_smu.h"
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#include "soc15_common.h"
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#include "vpe_v6_1.h"
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@ -33,8 +34,186 @@
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/* VPE CSA resides in the 4th page of CSA */
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#define AMDGPU_CSA_VPE_OFFSET (4096 * 3)
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/* 1 second timeout */
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#define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000)
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#define VPE_MAX_DPM_LEVEL 4
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#define FIXED1_8_BITS_PER_FRACTIONAL_PART 8
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#define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART)
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static void vpe_set_ring_funcs(struct amdgpu_device *adev);
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static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder)
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{
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*remainder = dividend % divisor;
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return dividend / divisor;
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}
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static inline uint16_t complete_integer_division_u16(
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uint16_t dividend,
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uint16_t divisor,
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uint16_t *remainder)
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{
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return div16_u16_rem(dividend, divisor, (uint16_t *)remainder);
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}
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static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator)
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{
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bool arg1_negative = numerator < 0;
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bool arg2_negative = denominator < 0;
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uint16_t arg1_value = (uint16_t)(arg1_negative ? -numerator : numerator);
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uint16_t arg2_value = (uint16_t)(arg2_negative ? -denominator : denominator);
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uint16_t remainder;
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/* determine integer part */
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uint16_t res_value = complete_integer_division_u16(
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arg1_value, arg2_value, &remainder);
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if (res_value > 127 /* CHAR_MAX */)
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return 0;
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/* determine fractional part */
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{
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unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART;
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do {
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remainder <<= 1;
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res_value <<= 1;
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if (remainder >= arg2_value) {
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res_value |= 1;
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remainder -= arg2_value;
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}
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} while (--i != 0);
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}
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/* round up LSB */
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{
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uint16_t summand = (remainder << 1) >= arg2_value;
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if ((res_value + summand) > 32767 /* SHRT_MAX */)
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return 0;
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res_value += summand;
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}
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if (arg1_negative ^ arg2_negative)
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res_value = -res_value;
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return res_value;
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}
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static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency)
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{
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uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency);
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if (GET_PRATIO_INTEGER_PART(pratio) > 1)
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pratio = 0;
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return pratio;
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}
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/*
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* VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),
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* VPE FW will dynamically decide which level should be used according to current loading.
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*
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* Get VPE and SOC clocks from PM, and select the appropriate four clock values,
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* calculate the ratios of adjusting from one clock to another.
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* The VPE FW can then request the appropriate frequency from the PMFW.
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*/
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int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
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{
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struct amdgpu_device *adev = vpe->ring.adev;
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uint32_t dpm_ctl;
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if (adev->pm.dpm_enabled) {
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struct dpm_clocks clock_table = { 0 };
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struct dpm_clock *VPEClks;
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struct dpm_clock *SOCClks;
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uint32_t idx;
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uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;
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uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;
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dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
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dpm_ctl |= 1; /* DPM enablement */
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
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/* Get VPECLK and SOCCLK */
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if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) {
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dev_dbg(adev->dev, "%s: get clock failed!\n", __func__);
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goto disable_dpm;
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}
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SOCClks = clock_table.SocClocks;
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VPEClks = clock_table.VPEClocks;
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/* vpe dpm only cares 4 levels. */
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for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) {
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uint32_t soc_dpm_level;
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uint32_t min_freq;
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if (idx == 0)
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soc_dpm_level = 0;
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else
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soc_dpm_level = (idx * 2) + 1;
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/* clamp the max level */
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if (soc_dpm_level > PP_SMU_NUM_VPECLK_DPM_LEVELS - 1)
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soc_dpm_level = PP_SMU_NUM_VPECLK_DPM_LEVELS - 1;
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min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ?
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SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;
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switch (idx) {
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case 0:
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pratio_vmin_freq = min_freq;
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break;
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case 1:
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pratio_vmid_freq = min_freq;
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break;
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case 2:
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pratio_vnorm_freq = min_freq;
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break;
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case 3:
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pratio_vmax_freq = min_freq;
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break;
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default:
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break;
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}
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}
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if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) {
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uint32_t pratio_ctl;
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pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);
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pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);
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pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);
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pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18);
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */
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dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__);
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} else {
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dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__);
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goto disable_dpm;
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}
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}
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return 0;
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disable_dpm:
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dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
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dpm_ctl &= 0xfffffffe; /* Disable DPM */
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
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dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
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return 0;
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}
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int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)
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{
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struct amdgpu_firmware_info ucode = {
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@ -134,6 +313,19 @@ static int vpe_early_init(void *handle)
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return 0;
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}
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static void vpe_idle_work_handler(struct work_struct *work)
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{
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, vpe.idle_work.work);
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unsigned int fences = 0;
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fences += amdgpu_fence_count_emitted(&adev->vpe.ring);
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if (fences == 0)
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
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else
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schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
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}
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static int vpe_common_init(struct amdgpu_vpe *vpe)
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{
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return r;
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}
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vpe->context_started = false;
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INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler);
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return 0;
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}
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@ -219,6 +414,9 @@ static int vpe_hw_fini(void *handle)
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vpe_ring_stop(vpe);
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/* Power off VPE */
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
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return 0;
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}
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@ -226,6 +424,8 @@ static int vpe_suspend(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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cancel_delayed_work_sync(&adev->vpe.idle_work);
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return vpe_hw_fini(adev);
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}
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static int vpe_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_vpe *vpe = &adev->vpe;
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if (!adev->pm.dpm_enabled)
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dev_err(adev->dev, "Without PM, cannot support powergating\n");
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dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE");
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if (state == AMD_PG_STATE_GATE) {
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amdgpu_dpm_enable_vpe(adev, false);
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vpe->context_started = false;
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} else {
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amdgpu_dpm_enable_vpe(adev, true);
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}
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return 0;
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}
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return ret;
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}
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static void vpe_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_vpe *vpe = &adev->vpe;
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cancel_delayed_work_sync(&adev->vpe.idle_work);
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/* Power on VPE and notify VPE of new context */
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if (!vpe->context_started) {
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uint32_t context_notify;
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/* Power on VPE */
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);
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/* Indicates that a job from a new context has been submitted. */
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context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));
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if ((context_notify & 0x1) == 0)
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context_notify |= 0x1;
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else
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context_notify &= ~(0x1);
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WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);
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vpe->context_started = true;
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}
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}
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static void vpe_ring_end_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
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}
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static const struct amdgpu_ring_funcs vpe_ring_funcs = {
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.type = AMDGPU_RING_TYPE_VPE,
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.align_mask = 0xf,
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.init_cond_exec = vpe_ring_init_cond_exec,
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.patch_cond_exec = vpe_ring_patch_cond_exec,
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.preempt_ib = vpe_ring_preempt_ib,
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.begin_use = vpe_ring_begin_use,
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.end_use = vpe_ring_end_use,
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};
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static void vpe_set_ring_funcs(struct amdgpu_device *adev)
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@ -47,6 +47,15 @@ struct vpe_regs {
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uint32_t queue0_rb_wptr_lo;
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uint32_t queue0_rb_wptr_hi;
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uint32_t queue0_preempt;
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uint32_t dpm_enable;
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uint32_t dpm_pratio;
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uint32_t dpm_request_interval;
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uint32_t dpm_decision_threshold;
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uint32_t dpm_busy_clamp_threshold;
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uint32_t dpm_idle_clamp_threshold;
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uint32_t dpm_request_lv;
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uint32_t context_indicator;
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};
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struct amdgpu_vpe {
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struct amdgpu_bo *cmdbuf_obj;
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uint64_t cmdbuf_gpu_addr;
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uint32_t *cmdbuf_cpu_addr;
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struct delayed_work idle_work;
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bool context_started;
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};
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int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);
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int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);
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int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);
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int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);
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int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);
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#define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ? (vpe)->funcs->ring_init((vpe)) : 0)
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#define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ? (vpe)->funcs->ring_start((vpe)) : 0)
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@ -96,6 +96,10 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
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adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
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amdgpu_vpe_psp_update_sram(adev);
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/* Config DPM */
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amdgpu_vpe_configure_dpm(vpe);
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return 0;
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}
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}
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vpe_v6_1_halt(vpe, false);
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/* Config DPM */
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amdgpu_vpe_configure_dpm(vpe);
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return 0;
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}
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vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;
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vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;
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vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;
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vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;
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vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;
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vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;
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vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;
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vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;
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vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;
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vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;
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return 0;
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}
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