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Qualcomm ARM64 DTS updates for 6.1

Browse source 
Support for Samsung Galaxy E5, E7 and Grand Max is added, with support
 for both 32-bit and 64-bit variants. The Samsung Galaxy S4 Mini Value
 Edition gains magnetometer support.
 
 MSM8996-based Xiaomi devices gains descriptions of the LPG-based LEDs.
 
 On SA8295P ADP problems arising from regulators being switched into
 low-power mode is worked around by removing this ability, for now.
 
 The onboard USB Hub on SC7180 Trogdor is finally described and a few ADC
 related updates are introduced.
 
 On SC7280 support for the CPU and LLC bwmon instances are introduced.
 Soundwire, audio codecs and sound introduced for a variety of boards.
 Using required-opps the USB controllers votes for a minimum corner on
 VDD_CX.
 The onboard USB Hub Herobrine is described. A new board, the Google
 Evoker is added, as is another revision of Herobrine Villager.
 
 On SC8280XP the USB controllers are marked as wakeup-sources, to keep
 them powered during suspend. The CRD has HID devices marked as
 wakeup-sources to enable resuming the system. In addition to these
 changes the alternative touchpad is introduced on the Lenovo ThinkPad
 X13s.
 
 SDM845 gains RPMh stats support and the LLCC BWMON is added. For SM6350
 interconnect providers and GPI DMA is introduced. A description of the
 PM7280b PMIC is added to Fairphone FP4 on SM7225.
 
 With the multi-MSI support added in the PCIe controller, SM8250 gets all
 its MSI interrupts added.
 
 UFS ICE and the second SDHCI controller is introduced on SM8450. Support
 for the Sony Xperia 1 IV is introduced.
 
 Throughout a variety of platforms the TCSR mutex syscon is replaced with
 the MMIO-based binding. TCSR nodes gained proper compatibles and halt
 syscon nodes are split out from the mutex ranges.
 
 A range of fixes to align with DT bindings are introduced. Among these
 are the changes to the follow the TLMM binding and suffix pinctrl states
 with -state and subnodes thereof with -pins, another is a number of
 changes transitioning to use -gpios and introduction of proper parent
 clock references in various clock providers.
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Merge tag 'qcom-arm64-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DTS updates for 6.1

Support for Samsung Galaxy E5, E7 and Grand Max is added, with support
for both 32-bit and 64-bit variants. The Samsung Galaxy S4 Mini Value
Edition gains magnetometer support.

MSM8996-based Xiaomi devices gains descriptions of the LPG-based LEDs.

On SA8295P ADP problems arising from regulators being switched into
low-power mode is worked around by removing this ability, for now.

The onboard USB Hub on SC7180 Trogdor is finally described and a few ADC
related updates are introduced.

On SC7280 support for the CPU and LLC bwmon instances are introduced.
Soundwire, audio codecs and sound introduced for a variety of boards.
Using required-opps the USB controllers votes for a minimum corner on
VDD_CX.
The onboard USB Hub Herobrine is described. A new board, the Google
Evoker is added, as is another revision of Herobrine Villager.

On SC8280XP the USB controllers are marked as wakeup-sources, to keep
them powered during suspend. The CRD has HID devices marked as
wakeup-sources to enable resuming the system. In addition to these
changes the alternative touchpad is introduced on the Lenovo ThinkPad
X13s.

SDM845 gains RPMh stats support and the LLCC BWMON is added. For SM6350
interconnect providers and GPI DMA is introduced. A description of the
PM7280b PMIC is added to Fairphone FP4 on SM7225.

With the multi-MSI support added in the PCIe controller, SM8250 gets all
its MSI interrupts added.

UFS ICE and the second SDHCI controller is introduced on SM8450. Support
for the Sony Xperia 1 IV is introduced.

Throughout a variety of platforms the TCSR mutex syscon is replaced with
the MMIO-based binding. TCSR nodes gained proper compatibles and halt
syscon nodes are split out from the mutex ranges.

A range of fixes to align with DT bindings are introduced. Among these
are the changes to the follow the TLMM binding and suffix pinctrl states
with -state and subnodes thereof with -pins, another is a number of
changes transitioning to use -gpios and introduction of proper parent
clock references in various clock providers.

* tag 'qcom-arm64-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (136 commits)
  arm64: dts: qcom: sc7280: Add required-opps for USB
  arm64: dts: qcom: sm8450: fix UFS PHY serdes size
  arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size
  arm64: dts: qcom: sa8295p-adp: add missing gpio-ranges in PMIC GPIOs
  arm64: dts: qcom: sa8295p-adp: add fallback compatible to PMIC GPIOs
  arm64: dts: qcom: msm8996-xiaomi: align PMIC GPIO pin configuration with DT schema
  arm64: dts: qcom: msm8994-msft-lumia-octagon: align resin node name with bindings
  arm64: dts: qcom: pmi8994: add missing MPP compatible fallback
  dt-bindings: pci: QCOM Add missing sc7280 aggre0, aggre1 clocks
  arm64: dts: qcom: sc7280: Add missing aggre0, aggre1 clocks
  arm64: dts: qcom: sc7280-villager: Adjust LTE SKUs
  dt-bindings: arm: qcom: Adjust LTE SKUs for sc7280-villager
  arm64: dts: qcom: sc7280-herobrine: Add nodes for onboard USB hub
  arm64: dts: qcom: sc7180-trogdor: Add nodes for onboard USB hub
  arm64: dts: qcom: align SDHCI reg-names with DT schema
  arm64: dts: qcom: sm8250: provide additional MSI interrupts
  arm64: dts: qcom: msm8996: add #clock-cells and XO clock to the HDMI PHY node
  arm64: dts: qcom: Use WCD9335 DT bindings
  arm64: dts: qcom: msm8994: switch TCSR mutex to MMIO
  arm64: dts: qcom: ipq6018: switch TCSR mutex to MMIO
  ...

Link: https://lore.kernel.org/r/20220921234854.1343238-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-09-23 16:36:42 +02:00
commit 6972b275fe
106 changed files with 3724 additions and 996 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
Documentation/devicetree/bindings/arm/qcom.yaml
View file

@ -176,6 +176,9 @@ properties:
- longcheer,l8910 - longcheer,l8910
- samsung,a3u-eur - samsung,a3u-eur
- samsung,a5u-eur - samsung,a5u-eur
- samsung,e5
- samsung,e7
- samsung,grandmax
- samsung,j5 - samsung,j5
- samsung,serranove - samsung,serranove
- wingtech,wt88047 - wingtech,wt88047
@ -450,6 +453,7 @@ properties:
- description: Google Pazquel with LTE and Parade (newest rev) - description: Google Pazquel with LTE and Parade (newest rev)
items: items:
- const: google,pazquel-sku6
- const: google,pazquel-sku4 - const: google,pazquel-sku4
- const: qcom,sc7180 - const: qcom,sc7180
@ -550,6 +554,7 @@ properties:
- description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev)
items: items:
- const: google,zoglin
- const: google,hoglin - const: google,hoglin
- const: qcom,sc7280 - const: qcom,sc7280
@ -565,16 +570,31 @@ properties:
- const: google,piglin - const: google,piglin
- const: qcom,sc7280 - const: qcom,sc7280
- description: Google Evoker (newest rev)
items:
- const: google,evoker
- const: qcom,sc7280
- description: Google Herobrine (newest rev) - description: Google Herobrine (newest rev)
items: items:
- const: google,herobrine - const: google,herobrine
- const: qcom,sc7280 - const: qcom,sc7280
- description: Google Villager (rev0)
items:
- const: google,villager-rev0
- const: qcom,sc7280
- description: Google Villager (newest rev) - description: Google Villager (newest rev)
items: items:
- const: google,villager - const: google,villager
- const: qcom,sc7280 - const: qcom,sc7280
- description: Google Villager with LTE (newest rev)
items:
- const: google,villager-sku512
- const: qcom,sc7280
- items: - items:
- enum: - enum:
- lenovo,flex-5g - lenovo,flex-5g
@ -716,6 +736,7 @@ properties:
- enum: - enum:
- qcom,sm8450-hdk - qcom,sm8450-hdk
- qcom,sm8450-qrd - qcom,sm8450-qrd
- sony,pdx223
- const: qcom,sm8450 - const: qcom,sm8450
additionalProperties: true additionalProperties: true

6
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
View file

@ -36,13 +36,11 @@ properties:
items: items:
- description: LPASS qdsp6ss register - description: LPASS qdsp6ss register
- description: LPASS top-cc register - description: LPASS top-cc register
- description: LPASS cc register
reg-names: reg-names:
items: items:
- const: qdsp6ss - const: qdsp6ss
- const: top_cc - const: top_cc
- const: cc
required: required:
- compatible - compatible
@ -59,8 +57,8 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h> #include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 { clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc"; compatible = "qcom,sc7280-lpasscc";
reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; reg = <0x03000000 0x40>, <0x03c04000 0x4>;
reg-names = "qdsp6ss", "top_cc", "cc"; reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface"; clock-names = "iface";
#clock-cells = <1>; #clock-cells = <1>;

26
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
View file

@ -22,6 +22,8 @@ properties:
clock-names: true clock-names: true
reg: true
compatible: compatible:
enum: enum:
- qcom,sc7280-lpassaoncc - qcom,sc7280-lpassaoncc
@ -38,8 +40,14 @@ properties:
'#power-domain-cells': '#power-domain-cells':
const: 1 const: 1
reg: '#reset-cells':
maxItems: 1 const: 1
qcom,adsp-pil-mode:
description:
Indicates if the LPASS would be brought out of reset using
peripheral loader.
type: boolean
required: required:
- compatible - compatible
@ -69,6 +77,11 @@ allOf:
items: items:
- const: bi_tcxo - const: bi_tcxo
- const: lpass_aon_cc_main_rcg_clk_src - const: lpass_aon_cc_main_rcg_clk_src
reg:
items:
- description: lpass core cc register
- description: lpass audio csr register
- if: - if:
properties: properties:
compatible: compatible:
@ -90,6 +103,8 @@ allOf:
- const: bi_tcxo_ao - const: bi_tcxo_ao
- const: iface - const: iface
reg:
maxItems: 1
- if: - if:
properties: properties:
compatible: compatible:
@ -108,6 +123,8 @@ allOf:
items: items:
- const: bi_tcxo - const: bi_tcxo
reg:
maxItems: 1
examples: examples:
- | - |
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
@ -116,13 +133,15 @@ examples:
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 { lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc"; compatible = "qcom,sc7280-lpassaudiocc";
reg = <0x3300000 0x30000>; reg = <0x3300000 0x30000>,
<0x32a9000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>; #clock-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
#reset-cells = <1>;
}; };
- | - |
@ -165,6 +184,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>; <&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface"; clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
qcom,adsp-pil-mode;
#clock-cells = <1>; #clock-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
}; };

8
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
View file

@ -18,6 +18,13 @@ properties:
oneOf: oneOf:
- items: - items:
- enum: - enum:
- qcom,msm8998-tcsr
- qcom,qcs404-tcsr
- qcom,sc7180-tcsr
- qcom,sc7280-tcsr
- qcom,sdm630-tcsr
- qcom,sdm845-tcsr
- qcom,sm8150-tcsr
- qcom,tcsr-apq8064 - qcom,tcsr-apq8064
- qcom,tcsr-apq8084 - qcom,tcsr-apq8084
- qcom,tcsr-ipq8064 - qcom,tcsr-ipq8064
@ -27,6 +34,7 @@ properties:
- qcom,tcsr-msm8953 - qcom,tcsr-msm8953
- qcom,tcsr-msm8960 - qcom,tcsr-msm8960
- qcom,tcsr-msm8974 - qcom,tcsr-msm8974
- qcom,tcsr-msm8996
- const: syscon - const: syscon
- items: - items:
- const: qcom,tcsr-ipq6018 - const: qcom,tcsr-ipq6018

10
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
View file

@ -54,11 +54,11 @@ properties:
# Platform constraints are described later. # Platform constraints are described later.
clocks: clocks:
minItems: 3 minItems: 3
maxItems: 12 maxItems: 13
clock-names: clock-names:
minItems: 3 minItems: 3
maxItems: 12 maxItems: 13
resets: resets:
minItems: 1 minItems: 1
@ -424,8 +424,8 @@ allOf:
then: then:
properties: properties:
clocks: clocks:
minItems: 11 minItems: 13
maxItems: 11 maxItems: 13
clock-names: clock-names:
items: items:
- const: pipe # PIPE clock - const: pipe # PIPE clock
@ -439,6 +439,8 @@ allOf:
- const: slave_q2a # Slave Q2A clock - const: slave_q2a # Slave Q2A clock
- const: tbu # PCIe TBU clock - const: tbu # PCIe TBU clock
- const: ddrss_sf_tbu # PCIe SF TBU clock - const: ddrss_sf_tbu # PCIe SF TBU clock
- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
- const: aggre1 # Aggre NoC PCIe1 AXI clock
resets: resets:
maxItems: 1 maxItems: 1
reset-names: reset-names:

3
arch/arm/boot/dts/Makefile
View file

@ -1050,6 +1050,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq8064-rb3011.dtb \ qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \ qcom-msm8660-surf.dtb \
qcom-msm8916-samsung-e5.dtb \
qcom-msm8916-samsung-e7.dtb \
qcom-msm8916-samsung-grandmax.dtb \
qcom-msm8916-samsung-serranove.dtb \ qcom-msm8916-samsung-serranove.dtb \
qcom-msm8960-cdp.dtb \ qcom-msm8960-cdp.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \

3
arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts Normal file
View file

@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-e5.dts"
#include "qcom-msm8916-smp.dtsi"

3
arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts Normal file
View file

@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-e7.dts"
#include "qcom-msm8916-smp.dtsi"

3
arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts Normal file
View file

@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-grandmax.dts"
#include "qcom-msm8916-smp.dtsi"

7
arch/arm64/boot/dts/qcom/Makefile
View file

@ -15,6 +15,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
@ -101,8 +104,11 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb
@ -152,3 +158,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb

11
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
View file

@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h> #include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/sound/qcom,wcd9335.h>
/* /*
* GPIO name legend: proper name = the GPIO line is used as GPIO * GPIO name legend: proper name = the GPIO line is used as GPIO
@ -502,20 +503,20 @@ config {
&pcie0 { &pcie0 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>; vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>; vdda-supply = <&vreg_l28a_0p925>;
}; };
&pcie1 { &pcie1 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>; vdda-supply = <&vreg_l28a_0p925>;
}; };
&pcie2 { &pcie2 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>; vdda-supply = <&vreg_l28a_0p925>;
}; };
@ -1064,7 +1065,7 @@ platform {
}; };
codec { codec {
sound-dai = <&wcd9335 6>; sound-dai = <&wcd9335 AIF4_PB>;
}; };
}; };
@ -1079,7 +1080,7 @@ platform {
}; };
codec { codec {
sound-dai = <&wcd9335 1>; sound-dai = <&wcd9335 AIF1_CAP>;
}; };
}; };
}; };

2
arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
View file

@ -368,7 +368,7 @@ &sdhc2 {
bus-width = <4>; bus-width = <4>;
cd-gpios = <&tlmm 38 0x1>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l21a_2p95>; vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>;

15
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file

@ -129,12 +129,6 @@ scm {
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
pmuv8: pmu { pmuv8: pmu {
compatible = "arm,cortex-a53-pmu"; compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@ -252,13 +246,14 @@ gcc: gcc@1800000 {
#reset-cells = <1>; #reset-cells = <1>;
}; };
tcsr_mutex_regs: syscon@1905000 { tcsr_mutex: hwlock@1905000 {
compatible = "syscon"; compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0x0 0x01905000 0x0 0x8000>; reg = <0x0 0x01905000 0x0 0x1000>;
#hwlock-cells = <1>;
}; };
tcsr: syscon@1937000 { tcsr: syscon@1937000 {
compatible = "syscon"; compatible = "qcom,tcsr-ipq6018", "syscon";
reg = <0x0 0x01937000 0x0 0x21000>; reg = <0x0 0x01937000 0x0 0x21000>;
}; };

4
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View file

@ -51,12 +51,12 @@ &blsp1_uart5 {
&pcie0 { &pcie0 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 61 0x1>; perst-gpios = <&tlmm 61 0x1>;
}; };
&pcie1 { &pcie1 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 58 0x1>; perst-gpios = <&tlmm 58 0x1>;
}; };
&pcie_phy0 { &pcie_phy0 {

4
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
View file

@ -39,12 +39,12 @@ &blsp1_uart5 {
&pcie0 { &pcie0 {
status = "ok"; status = "ok";
perst-gpio = <&tlmm 58 0x1>; perst-gpios = <&tlmm 58 0x1>;
}; };
&pcie1 { &pcie1 {
status = "ok"; status = "ok";
perst-gpio = <&tlmm 61 0x1>; perst-gpios = <&tlmm 61 0x1>;
}; };
&pcie_phy0 { &pcie_phy0 {

6
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file

@ -199,7 +199,7 @@ qusb_phy_0: phy@79000 {
pcie_qmp0: phy@86000 { pcie_qmp0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy"; compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1000>; reg = <0x00086000 0x1c4>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
@ -227,7 +227,7 @@ pcie_phy0: phy@86200 {
pcie_qmp1: phy@8e000 { pcie_qmp1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy"; compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x0008e000 0x1000>; reg = <0x0008e000 0x1c4>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
@ -383,7 +383,7 @@ spmi_bus: spmi@200f000 {
sdhc_1: mmc@7824900 { sdhc_1: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4"; compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>; reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
View file

@ -61,9 +61,9 @@ event-hall-sensor {
}; };
}; };
reg_vdd_tsp: regulator-vdd-tsp { reg_vdd_tsp_a: regulator-vdd-tsp-a {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vdd_tsp"; regulator-name = "vdd_tsp_a";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;

4
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
View file

@ -73,8 +73,8 @@ touchscreen@20 {
touchscreen-size-x = <540>; touchscreen-size-x = <540>;
touchscreen-size-y = <960>; touchscreen-size-y = <960>;
vdd-supply = <&reg_vdd_tsp>; vcca-supply = <&reg_vdd_tsp_a>;
vddo-supply = <&pm8916_l6>; vdd-supply = <&pm8916_l6>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ts_int_default>; pinctrl-0 = <&ts_int_default>;

2
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
View file

@ -42,7 +42,7 @@ touchscreen@48 {
touchscreen-size-x = <720>; touchscreen-size-x = <720>;
touchscreen-size-y = <1280>; touchscreen-size-y = <1280>;
avdd-supply = <&reg_vdd_tsp>; avdd-supply = <&reg_vdd_tsp_a>;
vdd-supply = <&pm8916_l6>; vdd-supply = <&pm8916_l6>;
pinctrl-names = "default"; pinctrl-names = "default";

85
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi Normal file
View file

@ -0,0 +1,85 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-samsung-a2015-common.dtsi"
/ {
haptic {
compatible = "regulator-haptic";
haptic-supply = <&reg_motor_vdd>;
min-microvolt = <3300000>;
max-microvolt = <3300000>;
};
i2c-muic {
/* SM5504 MUIC instead of SM5502 */
/delete-node/ extcon@25;
muic: extcon@14 {
compatible = "siliconmitus,sm5504-muic";
reg = <0x14>;
interrupt-parent = <&msmgpio>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&muic_int_default>;
};
};
reg_motor_vdd: regulator-motor-vdd {
compatible = "regulator-fixed";
regulator-name = "motor_vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&motor_en_default>;
};
reg_touch_key: regulator-touch-key {
compatible = "regulator-fixed";
regulator-name = "touch_key";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&tkey_en_default>;
};
};
&blsp_i2c2 {
/* lis2hh12 accelerometer instead of BMC150 */
status = "disabled";
/delete-node/ accelerometer@10;
/delete-node/ magnetometer@12;
};
&touchkey {
vcc-supply = <&reg_touch_key>;
vdd-supply = <&reg_touch_key>;
};
&msmgpio {
motor_en_default: motor-en-default {
pins = "gpio76";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tkey_en_default: tkey-en-default {
pins = "gpio97";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

24
arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-e2015-common.dtsi"
/*
* NOTE: The original firmware from Samsung can only boot ARM32 kernels on some
* variants.
* Unfortunately, the firmware is signed and cannot be replaced easily.
* There seems to be no way to boot ARM64 kernels on 32-bit devices at the
* moment, even though the hardware would support it.
*
* However, it is possible to use this device tree by compiling an ARM32 kernel
* instead. For clarity and build testing this device tree is maintained next
* to the other MSM8916 device trees. However, it is actually used through
* arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts
*/
/ {
model = "Samsung Galaxy E5";
compatible = "samsung,e5", "qcom,msm8916";
chassis-type = "handset";
};

29
arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts Normal file
View file

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-e2015-common.dtsi"
/*
* NOTE: The original firmware from Samsung can only boot ARM32 kernels on some
* variants.
* Unfortunately, the firmware is signed and cannot be replaced easily.
* There seems to be no way to boot ARM64 kernels on 32-bit devices at the
* moment, even though the hardware would support it.
*
* However, it is possible to use this device tree by compiling an ARM32 kernel
* instead. For clarity and build testing this device tree is maintained next
* to the other MSM8916 device trees. However, it is actually used through
* arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts
*/
/ {
model = "Samsung Galaxy E7";
compatible = "samsung,e7", "qcom,msm8916";
chassis-type = "handset";
};
&pm8916_l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};

60
arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts Normal file
View file

@ -0,0 +1,60 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-e2015-common.dtsi"
#include <dt-bindings/leds/common.h>
/*
* NOTE: The original firmware from Samsung can only boot ARM32 kernels on some
* variants.
* Unfortunately, the firmware is signed and cannot be replaced easily.
* There seems to be no way to boot ARM64 kernels on 32-bit devices at the
* moment, even though the hardware would support it.
*
* However, it is possible to use this device tree by compiling an ARM32 kernel
* instead. For clarity and build testing this device tree is maintained next
* to the other MSM8916 device trees. However, it is actually used through
* arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts
*/
/ {
model = "Samsung Galaxy Grand Max";
compatible = "samsung,grandmax", "qcom,msm8916";
chassis-type = "handset";
/delete-node/ gpio-hall-sensor;
/delete-node/ i2c-nfc;
/delete-node/ i2c-tkey;
gpio-leds {
compatible = "gpio-leds";
keyled {
gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&gpio_leds_default>;
};
};
};
&reg_motor_vdd {
gpio = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
};
&reg_touch_key {
status = "disabled";
};
&msmgpio {
gpio_leds_default: gpio-led-default {
pins = "gpio60";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
&motor_en_default {
pins = "gpio72";
};

9
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
View file

@ -210,6 +210,15 @@ imu@6b {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&imu_irq_default>; pinctrl-0 = <&imu_irq_default>;
}; };
magnetometer@2e {
compatible = "yamaha,yas537";
reg = <0x2e>;
mount-matrix = "0", "1", "0",
"1", "0", "0",
"0", "0", "-1";
};
}; };
&blsp_i2c4 { &blsp_i2c4 {

18
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -936,6 +936,20 @@ gcc: clock-controller@1800000 {
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
reg = <0x01800000 0x80000>; reg = <0x01800000 0x80000>;
clocks = <&xo_board>,
<&sleep_clk>,
<&dsi_phy0 1>,
<&dsi_phy0 0>,
<0>,
<0>,
<0>;
clock-names = "xo",
"sleep_clk",
"dsi0pll",
"dsi0pllbyte",
"ext_mclk",
"ext_pri_i2s",
"ext_sec_i2s";
}; };
tcsr_mutex: hwlock@1905000 { tcsr_mutex: hwlock@1905000 {
@ -1469,7 +1483,7 @@ lpass_codec: audio-codec@771c000 {
sdhc_1: mmc@7824000 { sdhc_1: mmc@7824000 {
compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg = <0x07824900 0x11c>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@ -1487,7 +1501,7 @@ sdhc_1: mmc@7824000 {
sdhc_2: mmc@7864000 { sdhc_2: mmc@7864000 {
compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm64/boot/dts/qcom/msm8953.dtsi
View file

@ -722,7 +722,7 @@ tcsr: syscon@1937000 {
}; };
tcsr_phy_clk_scheme_sel: syscon@193f044 { tcsr_phy_clk_scheme_sel: syscon@193f044 {
compatible = "syscon"; compatible = "qcom,tcsr-msm8953", "syscon";
reg = <0x193f044 0x4>; reg = <0x193f044 0x4>;
}; };
@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 {
compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>; reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 {
compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7864900 0x500>, <0x7864000 0x800>; reg = <0x7864900 0x500>, <0x7864000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View file

@ -17,7 +17,7 @@ / {
chassis-type = "handset"; chassis-type = "handset";
/* required for bootloader to select correct board */ /* required for bootloader to select correct board */
qcom,msm-id = <251 0 252 0>; qcom,msm-id = <251 0>, <252 0>;
qcom,pmic-id = <65545 65546 0 0>; qcom,pmic-id = <65545 65546 0 0>;
qcom,board-id = <12 0>; qcom,board-id = <12 0>;

2
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
View file

@ -499,7 +499,7 @@ pwrkey {
linux,code = <KEY_POWER>; linux,code = <KEY_POWER>;
}; };
volwnkey { resin {
compatible = "qcom,pm8941-resin"; compatible = "qcom,pm8941-resin";
interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>; interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>; debounce = <15625>;

2
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View file

@ -471,7 +471,7 @@ &sdhc1 {
&sdhc2 { &sdhc2 {
status = "okay"; status = "okay";
cd-gpios = <&tlmm 100 0>; cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&pm8994_l21>; vmmc-supply = <&pm8994_l21>;
vqmmc-supply = <&pm8994_l13>; vqmmc-supply = <&pm8994_l13>;
}; };

20
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file

@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h> #include <dt-bindings/clock/qcom,gcc-msm8994.h>
#include <dt-bindings/clock/qcom,mmcc-msm8994.h> #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
/ { / {
@ -164,12 +165,6 @@ memory@80000000 {
reg = <0 0x80000000 0 0>; reg = <0 0x80000000 0 0>;
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
pmu { pmu {
compatible = "arm,cortex-a53-pmu"; compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
@ -464,7 +459,7 @@ usb@f9200000 {
sdhc1: mmc@f9824900 { sdhc1: mmc@f9824900 {
compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@ -487,7 +482,7 @@ sdhc1: mmc@f9824900 {
sdhc2: mmc@f98a4900 { sdhc2: mmc@f98a4900 {
compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@ -502,7 +497,7 @@ sdhc2: mmc@f98a4900 {
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
cd-gpios = <&tlmm 100 0>; cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
bus-width = <4>; bus-width = <4>;
status = "disabled"; status = "disabled";
}; };
@ -762,9 +757,10 @@ spmi_bus: spmi@fc4c0000 {
#interrupt-cells = <4>; #interrupt-cells = <4>;
}; };
tcsr_mutex_regs: syscon@fd484000 { tcsr_mutex: hwlock@fd484000 {
compatible = "syscon"; compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0xfd484000 0x2000>; reg = <0xfd484000 0x1000>;
#hwlock-cells = <1>;
}; };
tlmm: pinctrl@fd510000 { tlmm: pinctrl@fd510000 {

4
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
View file

@ -196,8 +196,8 @@ &mmcc {
&pcie0 { &pcie0 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&wlan_en>; vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>; vdda-supply = <&pm8994_l28>;
}; };

52
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View file

@ -58,6 +58,14 @@ key-dome {
}; };
}; };
irled {
compatible = "pwm-ir-tx";
pwms = <&pm8994_lpg 1 1000000>;
pinctrl-names = "default";
pinctrl-0 = <&irled_default>;
};
reserved-memory { reserved-memory {
memory@88800000 { memory@88800000 {
reg = <0x0 0x88800000 0x0 0x1400000>; reg = <0x0 0x88800000 0x0 0x1400000>;
@ -297,6 +305,41 @@ &pm8994_resin {
linux,code = <KEY_VOLUMEDOWN>; linux,code = <KEY_VOLUMEDOWN>;
}; };
&pm8994_lpg {
status = "okay";
qcom,power-source = <1>;
};
&pmi8994_lpg {
status = "okay";
qcom,power-source = <1>;
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
color = <LED_COLOR_ID_BLUE>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_RED>;
};
};
};
&slpi_pil { &slpi_pil {
status = "okay"; status = "okay";
@ -608,6 +651,15 @@ vdd_gfx: s2 {
}; };
&pm8994_gpios { &pm8994_gpios {
irled_default: irled-default-state {
pins = "gpio5";
function = PMIC_GPIO_FUNC_FUNC1;
output-low;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
power-source = <PM8994_GPIO_S4>;
bias-disable;
};
wlan_en_default: wlan-en-state { wlan_en_default: wlan-en-state {
pins = "gpio8"; pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL; function = PMIC_GPIO_FUNC_NORMAL;

5
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View file

@ -8,6 +8,7 @@
#include "msm8996-xiaomi-common.dtsi" #include "msm8996-xiaomi-common.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h> #include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/sound/qcom,wcd9335.h>
#include <dt-bindings/input/ti-drv260x.h> #include <dt-bindings/input/ti-drv260x.h>
/ { / {
@ -193,7 +194,7 @@ platform {
}; };
codec { codec {
sound-dai = <&wcd9335 6>; sound-dai = <&wcd9335 AIF4_PB>;
}; };
}; };
@ -208,7 +209,7 @@ platform {
}; };
codec { codec {
sound-dai = <&wcd9335 1>; sound-dai = <&wcd9335 AIF1_CAP>;
}; };
}; };
}; };

33
arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts
View file

@ -9,6 +9,7 @@
#include "pmi8996.dtsi" #include "pmi8996.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h> #include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/sound/qcom,wcd9335.h>
/ { / {
model = "Xiaomi Mi Note 2"; model = "Xiaomi Mi Note 2";
@ -116,6 +117,25 @@ &mss_pil {
"qcom/msm8996/scorpio/modem.mbn"; "qcom/msm8996/scorpio/modem.mbn";
}; };
&pm8994_lpg {
pinctrl-names = "default";
pinctrl-0 = <&keypad_default>;
led@3 {
reg = <3>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_KBD_BACKLIGHT;
function-enumerator = <1>;
};
led@6 {
reg = <6>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_KBD_BACKLIGHT;
function-enumerator = <0>;
};
};
&q6asmdai { &q6asmdai {
dai@0 { dai@0 {
reg = <0>; reg = <0>;
@ -171,7 +191,7 @@ platform {
}; };
codec { codec {
sound-dai = <&wcd9335 6>; sound-dai = <&wcd9335 AIF4_PB>;
}; };
}; };
@ -186,7 +206,7 @@ platform {
}; };
codec { codec {
sound-dai = <&wcd9335 1>; sound-dai = <&wcd9335 AIF1_CAP>;
}; };
}; };
}; };
@ -258,6 +278,15 @@ &pm8994_gpios {
"PMIC_SLB", /* GPIO_20 */ "PMIC_SLB", /* GPIO_20 */
"UIM_BATT_ALARM", /* GPIO_21 */ "UIM_BATT_ALARM", /* GPIO_21 */
"NC"; /* GPIO_22 */ "NC"; /* GPIO_22 */
keypad_default: keypad-default-state {
pins = "gpio7", "gpio10";
function = PMIC_GPIO_FUNC_FUNC1;
output-low;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
power-source = <PM8994_GPIO_S4>;
bias-disable;
};
}; };
&pm8994_mpps { &pm8994_mpps {

41
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file

@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,msm8996.h> #include <dt-bindings/interconnect/qcom,msm8996.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
@ -359,16 +360,10 @@ opp-2150400000 {
firmware { firmware {
scm { scm {
compatible = "qcom,scm-msm8996", "qcom,scm"; compatible = "qcom,scm-msm8996", "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>; qcom,dload-mode = <&tcsr_2 0x13000>;
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
/* We expect the bootloader to fill in the reg */ /* We expect the bootloader to fill in the reg */
@ -838,12 +833,18 @@ pnoc: interconnect@5c0000 {
<&rpmcc RPM_SMD_PCNOC_A_CLK>; <&rpmcc RPM_SMD_PCNOC_A_CLK>;
}; };
tcsr_mutex_regs: syscon@740000 { tcsr_mutex: hwlock@740000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0x00740000 0x40000>; reg = <0x00740000 0x20000>;
#hwlock-cells = <1>;
}; };
tcsr: syscon@7a0000 { tcsr_1: syscon@760000 {
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x00760000 0x20000>;
};
tcsr_2: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon"; compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x007a0000 0x18000>; reg = <0x007a0000 0x18000>;
}; };
@ -1161,9 +1162,13 @@ hdmi_phy: hdmi-phy@9a0600 {
"hdmi_phy"; "hdmi_phy";
clocks = <&mmcc MDSS_AHB_CLK>, clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>; <&gcc GCC_HDMI_CLKREF_CLK>,
<&xo_board>;
clock-names = "iface", clock-names = "iface",
"ref"; "ref",
"xo";
#clock-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -2413,7 +2418,7 @@ mss_pil: remoteproc@2080000 {
qcom,smem-states = <&mpss_smp2p_out 0>; qcom,smem-states = <&mpss_smp2p_out 0>;
qcom,smem-state-names = "stop"; qcom,smem-state-names = "stop";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
status = "disabled"; status = "disabled";
@ -3018,7 +3023,7 @@ hsusb_phy2: phy@7412000 {
sdhc1: mmc@7464900 { sdhc1: mmc@7464900 {
compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07464900 0x11c>, <0x07464000 0x800>; reg = <0x07464900 0x11c>, <0x07464000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
@ -3042,7 +3047,7 @@ sdhc1: mmc@7464900 {
sdhc2: mmc@74a4900 { sdhc2: mmc@74a4900 {
compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
reg = <0x074a4900 0x314>, <0x074a4000 0x800>; reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@ -3337,7 +3342,7 @@ wcd9335: codec@1{
interrupt-names = "intr1", "intr2"; interrupt-names = "intr1", "intr2";
interrupt-controller; interrupt-controller;
#interrupt-cells = <1>; #interrupt-cells = <1>;
reset-gpios = <&tlmm 64 0>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
slim-ifc-dev = <&tasha_ifd>; slim-ifc-dev = <&tasha_ifd>;
@ -3499,7 +3504,7 @@ frame@98c0000 {
}; };
saw3: syscon@9a10000 { saw3: syscon@9a10000 {
compatible = "syscon"; compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x09a10000 0x1000>; reg = <0x09a10000 0x1000>;
}; };

24
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file

@ -308,12 +308,6 @@ scm {
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
psci { psci {
compatible = "arm,psci-1.0"; compatible = "arm,psci-1.0";
method = "smc"; method = "smc";
@ -1047,9 +1041,15 @@ ufsphy_lanes: phy@1da7400 {
}; };
}; };
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex: hwlock@1f40000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>; reg = <0x01f40000 0x20000>;
#hwlock-cells = <1>;
};
tcsr_regs_1: syscon@1f60000 {
compatible = "qcom,msm8998-tcsr", "syscon";
reg = <0x01f60000 0x20000>;
}; };
tlmm: pinctrl@3400000 { tlmm: pinctrl@3400000 {
@ -1340,7 +1340,7 @@ remoteproc_mss: remoteproc@4080000 {
resets = <&gcc GCC_MSS_RESTART>; resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart"; reset-names = "mss_restart";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
power-domains = <&rpmpd MSM8998_VDDCX>, power-domains = <&rpmpd MSM8998_VDDCX>,
<&rpmpd MSM8998_VDDMX>; <&rpmpd MSM8998_VDDMX>;
@ -2076,9 +2076,9 @@ qusb2phy: phy@c012000 {
}; };
sdhc2: mmc@c0a4900 { sdhc2: mmc@c0a4900 {
compatible = "qcom,sdhci-msm-v4"; compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
reg-names = "hc_mem", "core_mem"; reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

19
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View file

@ -20,10 +20,29 @@ pm6150l_adc: adc@3100 {
#size-cells = <0>; #size-cells = <0>;
#io-channel-cells = <1>; #io-channel-cells = <1>;
adc-chan@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
adc-chan@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
adc-chan@6 { adc-chan@6 {
reg = <ADC5_DIE_TEMP>; reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp"; label = "die_temp";
}; };
adc-chan@83 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
}; };
pm6150l_adc_tm: adc-tm@3500 { pm6150l_adc_tm: adc-tm@3500 {

2
arch/arm64/boot/dts/qcom/pm660.dtsi
View file

@ -187,7 +187,7 @@ pmic@1 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pm660_spmi_regulators: pm660-regulators { pm660_spmi_regulators: regulators {
compatible = "qcom,pm660-regulators"; compatible = "qcom,pm660-regulators";
}; };
}; };

4
arch/arm64/boot/dts/qcom/pm660l.dtsi
View file

@ -65,7 +65,7 @@ pmic@3 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pm660l_lpg: lpg@b100 { pm660l_lpg: pwm {
compatible = "qcom,pm660l-lpg"; compatible = "qcom,pm660l-lpg";
status = "disabled"; status = "disabled";
@ -81,7 +81,7 @@ pm660l_wled: leds@d800 {
status = "disabled"; status = "disabled";
}; };
pm660l_spmi_regulators: pm660l-regulators { pm660l_spmi_regulators: regulators {
compatible = "qcom,pm660l-regulators"; compatible = "qcom,pm660l-regulators";
}; };
}; };

149
arch/arm64/boot/dts/qcom/pm7250b.dtsi Normal file
View file

@ -0,0 +1,149 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm7250b-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_temp>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@2 {
compatible = "qcom,pm7250b", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm7250b_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pm7250b_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm7250b_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
adc-chan@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
adc-chan@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
adc-chan@2 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
adc-chan@7 {
reg = <ADC5_USB_IN_I>;
qcom,pre-scaling = <1 1>;
label = "usb_in_i_uv";
};
adc-chan@8 {
reg = <ADC5_USB_IN_V_16>;
qcom,pre-scaling = <1 16>;
label = "usb_in_v_div_16";
};
adc-chan@9 {
reg = <ADC5_CHG_TEMP>;
qcom,pre-scaling = <1 1>;
label = "chg_temp";
};
adc-chan@e {
reg = <ADC5_AMUX_THM2>;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "smb1390_therm";
};
adc-chan@1e {
reg = <ADC5_MID_CHG_DIV6>;
qcom,pre-scaling = <1 6>;
label = "chg_mid";
};
adc-chan@83 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
adc-chan@84 {
reg = <ADC5_VBAT_SNS>;
qcom,pre-scaling = <1 3>;
label = "vbat_sns";
};
adc-chan@99 {
reg = <ADC5_SBUx>;
qcom,pre-scaling = <1 3>;
label = "chg_sbux";
};
};
pm7250b_adc_tm: adc-tm@3500 {
compatible = "qcom,spmi-adc-tm5";
reg = <0x3500>;
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
pmic@3 {
compatible = "qcom,pm7250b", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};

2
arch/arm64/boot/dts/qcom/pm8150.dtsi
View file

@ -47,7 +47,7 @@ pm8150_0: pmic@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pon: power-on@800 { pon: pon@800 {
compatible = "qcom,pm8998-pon"; compatible = "qcom,pm8998-pon";
reg = <0x0800>; reg = <0x0800>;
mode-bootloader = <0x2>; mode-bootloader = <0x2>;

4
arch/arm64/boot/dts/qcom/pm8150b.dtsi
View file

@ -46,7 +46,7 @@ pmic@2 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
power-on@800 { pon@800 {
compatible = "qcom,pm8916-pon"; compatible = "qcom,pm8916-pon";
reg = <0x0800>; reg = <0x0800>;
@ -128,7 +128,7 @@ pmic@3 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pm8150b_lpg: lpg { pm8150b_lpg: pwm {
compatible = "qcom,pm8150b-lpg"; compatible = "qcom,pm8150b-lpg";
#address-cells = <1>; #address-cells = <1>;

4
arch/arm64/boot/dts/qcom/pm8150l.dtsi
View file

@ -46,7 +46,7 @@ pmic@4 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
power-on@800 { pon@800 {
compatible = "qcom,pm8916-pon"; compatible = "qcom,pm8916-pon";
reg = <0x0800>; reg = <0x0800>;
@ -116,7 +116,7 @@ pmic@5 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pm8150l_lpg: lpg { pm8150l_lpg: pwm {
compatible = "qcom,pm8150l-lpg"; compatible = "qcom,pm8150l-lpg";
#address-cells = <1>; #address-cells = <1>;

3
arch/arm64/boot/dts/qcom/pm8350c.dtsi
View file

@ -30,9 +30,8 @@ pm8350c_gpios: gpio@8800 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
pm8350c_pwm: pwm@e800 { pm8350c_pwm: pwm {
compatible = "qcom,pm8350c-pwm"; compatible = "qcom,pm8350c-pwm";
reg = <0xe800>;
#pwm-cells = <2>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/qcom/pm8953.dtsi
View file

@ -45,7 +45,7 @@ temp-alarm@2400 {
#thermal-sensor-cells = <0>; #thermal-sensor-cells = <0>;
}; };
pm8953_vadc: vadc@3100 { pm8953_vadc: adc@3100 {
compatible = "qcom,spmi-vadc"; compatible = "qcom,spmi-vadc";
reg = <0x3100>; reg = <0x3100>;
interrupts = <0x00 0x31 0x00 0x01>; interrupts = <0x00 0x31 0x00 0x01>;

2
arch/arm64/boot/dts/qcom/pm8994.dtsi
View file

@ -135,7 +135,7 @@ pmic@1 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pm8994_lpg: lpg { pm8994_lpg: pwm {
compatible = "qcom,pm8994-lpg"; compatible = "qcom,pm8994-lpg";
#address-cells = <1>; #address-cells = <1>;

4
arch/arm64/boot/dts/qcom/pmi8994.dtsi
View file

@ -21,7 +21,7 @@ pmi8994_gpios: gpios@c000 {
}; };
pmi8994_mpps: mpps@a000 { pmi8994_mpps: mpps@a000 {
compatible = "qcom,pmi8994-mpp"; compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp";
reg = <0xa000>; reg = <0xa000>;
gpio-controller; gpio-controller;
gpio-ranges = <&pmi8994_mpps 0 0 4>; gpio-ranges = <&pmi8994_mpps 0 0 4>;
@ -37,7 +37,7 @@ pmic@3 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pmi8994_lpg: lpg { pmi8994_lpg: pwm {
compatible = "qcom,pmi8994-lpg"; compatible = "qcom,pmi8994-lpg";
#address-cells = <1>; #address-cells = <1>;

2
arch/arm64/boot/dts/qcom/pmi8998.dtsi
View file

@ -42,7 +42,7 @@ lab: lab {
}; };
}; };
pmi8998_lpg: lpg { pmi8998_lpg: pwm {
compatible = "qcom,pmi8998-lpg"; compatible = "qcom,pmi8998-lpg";
#address-cells = <1>; #address-cells = <1>;

3
arch/arm64/boot/dts/qcom/pmk8350.dtsi
View file

@ -39,16 +39,13 @@ pmk8350_vadc: adc@3100 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eoc-int-en-set";
#io-channel-cells = <1>; #io-channel-cells = <1>;
io-channel-ranges;
}; };
pmk8350_adc_tm: adc-tm@3400 { pmk8350_adc_tm: adc-tm@3400 {
compatible = "qcom,adc-tm7"; compatible = "qcom,adc-tm7";
reg = <0x3400>; reg = <0x3400>;
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "threshold";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;

2
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
View file

@ -46,7 +46,7 @@ pmic@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pon: power-on@800 { pon: pon@800 {
compatible = "qcom,pm8916-pon"; compatible = "qcom,pm8916-pon";
reg = <0x0800>; reg = <0x0800>;
pwrkey { pwrkey {

2
arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
View file

@ -45,7 +45,7 @@ pmic@4 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
power-on@800 { pon@800 {
compatible = "qcom,pm8916-pon"; compatible = "qcom,pm8916-pon";
reg = <0x0800>; reg = <0x0800>;

2
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View file

@ -99,7 +99,7 @@ pms405_s3: s3 {
&pcie { &pcie {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&perst_state>; pinctrl-0 = <&perst_state>;

15
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file

@ -295,12 +295,6 @@ smem {
hwlocks = <&tcsr_mutex 3>; hwlocks = <&tcsr_mutex 3>;
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
soc: soc@0 { soc: soc@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -726,13 +720,14 @@ gcc: clock-controller@1800000 {
assigned-clock-rates = <19200000>; assigned-clock-rates = <19200000>;
}; };
tcsr_mutex_regs: syscon@1905000 { tcsr_mutex: hwlock@1905000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0x01905000 0x20000>; reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
}; };
tcsr: syscon@1937000 { tcsr: syscon@1937000 {
compatible = "syscon"; compatible = "qcom,qcs404-tcsr", "syscon";
reg = <0x01937000 0x25000>; reg = <0x01937000 0x25000>;
}; };
@ -1297,7 +1292,7 @@ glink-edge {
}; };
pcie: pci@10000000 { pcie: pci@10000000 {
compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>, reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>, <0x10000f20 0xa8>,
<0x07780000 0x2000>, <0x07780000 0x2000>,

3
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View file

@ -333,9 +333,6 @@ &ethernet {
snps,reset-active-low; snps,reset-active-low;
snps,reset-delays-us = <0 11000 70000>; snps,reset-delays-us = <0 11000 70000>;
snps,ptp-ref-clk-rate = <250000000>;
snps,ptp-req-clk-rate = <96000000>;
snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>;

23
arch/arm64/boot/dts/qcom/sa8295p-adp.dts
View file

@ -35,7 +35,6 @@ vreg_l3a: ldo3 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1208000>; regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l5a: ldo5 { vreg_l5a: ldo5 {
@ -43,7 +42,6 @@ vreg_l5a: ldo5 {
regulator-min-microvolt = <912000>; regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>; regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l7a: ldo7 { vreg_l7a: ldo7 {
@ -51,7 +49,6 @@ vreg_l7a: ldo7 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l13a: ldo13 { vreg_l13a: ldo13 {
@ -59,7 +56,6 @@ vreg_l13a: ldo13 {
regulator-min-microvolt = <3072000>; regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>; regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
}; };
@ -72,7 +68,6 @@ vreg_l1c: ldo1 {
regulator-min-microvolt = <912000>; regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>; regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l2c: ldo2 { vreg_l2c: ldo2 {
@ -80,7 +75,6 @@ vreg_l2c: ldo2 {
regulator-min-microvolt = <3072000>; regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>; regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l3c: ldo3 { vreg_l3c: ldo3 {
@ -96,7 +90,6 @@ vreg_l4c: ldo4 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1208000>; regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l6c: ldo6 { vreg_l6c: ldo6 {
@ -112,7 +105,6 @@ vreg_l7c: ldo7 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l10c: ldo10 { vreg_l10c: ldo10 {
@ -141,7 +133,6 @@ vreg_l3g: ldo3 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l7g: ldo7 { vreg_l7g: ldo7 {
@ -149,7 +140,6 @@ vreg_l7g: ldo7 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l8g: ldo8 { vreg_l8g: ldo8 {
@ -157,7 +147,6 @@ vreg_l8g: ldo8 {
regulator-min-microvolt = <880000>; regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>; regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
}; };
}; };
@ -194,9 +183,10 @@ pm8450a: pmic@0 {
#size-cells = <0>; #size-cells = <0>;
pm8450a_gpios: gpio@c000 { pm8450a_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio"; compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>; reg = <0xc000>;
gpio-controller; gpio-controller;
gpio-ranges = <&pm8450a_gpios 0 0 10>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -210,9 +200,10 @@ pm8450c: pmic@4 {
#size-cells = <0>; #size-cells = <0>;
pm8450c_gpios: gpio@c000 { pm8450c_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio"; compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>; reg = <0xc000>;
gpio-controller; gpio-controller;
gpio-ranges = <&pm8450c_gpios 0 0 10>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -226,9 +217,10 @@ pm8450e: pmic@8 {
#size-cells = <0>; #size-cells = <0>;
pm8450e_gpios: gpio@c000 { pm8450e_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio"; compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>; reg = <0xc000>;
gpio-controller; gpio-controller;
gpio-ranges = <&pm8450e_gpios 0 0 10>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -242,9 +234,10 @@ pm8450g: pmic@c {
#size-cells = <0>; #size-cells = <0>;
pm8450g_gpios: gpio@c000 { pm8450g_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio"; compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>; reg = <0xc000>;
gpio-controller; gpio-controller;
gpio-ranges = <&pm8450g_gpios 0 0 10>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
View file

@ -24,8 +24,6 @@ &charger_thermal {
}; };
&pm6150_adc { &pm6150_adc {
status = "disabled";
/delete-node/ skin-temp-thermistor@4e; /delete-node/ skin-temp-thermistor@4e;
/delete-node/ charger-thermistor@4f; /delete-node/ charger-thermistor@4f;
}; };

19
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
View file

@ -16,17 +16,6 @@ / {
compatible = "google,lazor-rev0", "qcom,sc7180"; compatible = "google,lazor-rev0", "qcom,sc7180";
}; };
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
/delete-property/regulator-boot-on;
};
&pp3300_l7c {
regulator-always-on;
regulator-boot-on;
};
&sn65dsi86_out { &sn65dsi86_out {
/* /*
* Lane 0 was incorrectly mapped on the cable, but we've now decided * Lane 0 was incorrectly mapped on the cable, but we've now decided
@ -35,3 +24,11 @@ &sn65dsi86_out {
*/ */
lane-polarities = <1 0>; lane-polarities = <1 0>;
}; };
&usb_hub_2_x {
vdd-supply = <&pp3300_l7c>;
};
&usb_hub_3_x {
vdd-supply = <&pp3300_l7c>;
};

12
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts
View file

@ -16,13 +16,11 @@ / {
compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180";
}; };
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */ &usb_hub_2_x {
/delete-property/regulator-always-on; vdd-supply = <&pp3300_l7c>;
/delete-property/regulator-boot-on;
}; };
&pp3300_l7c { &usb_hub_3_x {
regulator-always-on; vdd-supply = <&pp3300_l7c>;
regulator-boot-on;
}; };

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View file

@ -55,8 +55,6 @@ &panel {
}; };
&pm6150_adc { &pm6150_adc {
status = "disabled";
/delete-node/ charger-thermistor@4f; /delete-node/ charger-thermistor@4f;
}; };

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts
View file

@ -14,7 +14,7 @@
/ { / {
model = "Google Pazquel (Parade,LTE)"; model = "Google Pazquel (Parade,LTE)";
compatible = "google,pazquel-sku4", "qcom,sc7180"; compatible = "google,pazquel-sku6", "google,pazquel-sku4", "qcom,sc7180";
}; };
&ap_sar_sensor_i2c { &ap_sar_sensor_i2c {

11
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts
View file

@ -34,13 +34,10 @@ &pm6150_adc_tm {
/delete-node/ charger-thermistor@0; /delete-node/ charger-thermistor@0;
}; };
&pp3300_hub { &usb_hub_2_x {
/* pp3300_l7c is used to power the USB hub */ vdd-supply = <&pp3300_l7c>;
/delete-property/regulator-always-on;
/delete-property/regulator-boot-on;
}; };
&pp3300_l7c { &usb_hub_3_x {
regulator-always-on; vdd-supply = <&pp3300_l7c>;
regulator-boot-on;
}; };

19
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
View file

@ -44,17 +44,6 @@ &panel {
compatible = "auo,b116xa01"; compatible = "auo,b116xa01";
}; };
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
/delete-property/regulator-boot-on;
};
&pp3300_l7c {
regulator-always-on;
regulator-boot-on;
};
&sdhc_2 { &sdhc_2 {
status = "okay"; status = "okay";
}; };
@ -63,6 +52,14 @@ &trackpad {
interrupts = <58 IRQ_TYPE_EDGE_FALLING>; interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
}; };
&usb_hub_2_x {
vdd-supply = <&pp3300_l7c>;
};
&usb_hub_3_x {
vdd-supply = <&pp3300_l7c>;
};
/* PINCTRL - modifications to sc7180-trogdor.dtsi */ /* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl { &trackpad_int_1v8_odl {

20
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View file

@ -299,7 +299,7 @@ pp3300_hub: pp3300-hub-regulator {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&en_pp3300_hub>; pinctrl-0 = <&en_pp3300_hub>;
regulator-always-on; /* The BIOS leaves this regulator on */
regulator-boot-on; regulator-boot-on;
vin-supply = <&pp3300_a>; vin-supply = <&pp3300_a>;
@ -936,6 +936,24 @@ &usb_1 {
&usb_1_dwc3 { &usb_1_dwc3 {
dr_mode = "host"; dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
/* 2.x hub on port 1 */
usb_hub_2_x: hub@1 {
compatible = "usbbda,5411";
reg = <1>;
vdd-supply = <&pp3300_hub>;
peer-hub = <&usb_hub_3_x>;
};
/* 3.x hub on port 2 */
usb_hub_3_x: hub@2 {
compatible = "usbbda,411";
reg = <2>;
vdd-supply = <&pp3300_hub>;
peer-hub = <&usb_hub_2_x>;
};
}; };
&usb_1_hsphy { &usb_1_hsphy {

26
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -555,12 +555,6 @@ scm {
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
smem { smem {
compatible = "qcom,smem"; compatible = "qcom,smem";
memory-region = <&smem_mem>; memory-region = <&smem_mem>;
@ -1462,13 +1456,19 @@ ipa: ipa@1e40000 {
status = "disabled"; status = "disabled";
}; };
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex: hwlock@1f40000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x40000>; reg = <0 0x01f40000 0 0x20000>;
#hwlock-cells = <1>;
}; };
tcsr_regs: syscon@1fc0000 { tcsr_regs_1: syscon@1f60000 {
compatible = "syscon"; compatible = "qcom,sc7180-tcsr", "syscon";
reg = <0 0x01f60000 0 0x20000>;
};
tcsr_regs_2: syscon@1fc0000 {
compatible = "qcom,sc7180-tcsr", "syscon";
reg = <0 0x01fc0000 0 0x40000>; reg = <0 0x01fc0000 0 0x40000>;
}; };
@ -1932,8 +1932,8 @@ remoteproc_mpss: remoteproc@4080000 {
<&pdc_reset PDC_MODEM_SYNC_RESET>; <&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset"; reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
qcom,spare-regs = <&tcsr_regs 0xb3e4>; qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
status = "disabled"; status = "disabled";

11
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View file

@ -83,17 +83,6 @@ spi_flash: flash@0 {
}; };
}; };
/* Modem setup is different on Chrome setups than typical Qualcomm setup */
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&mba_mem>, <&mpss_mem>;
firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn",
"qcom/sc7280-herobrine/modem/qdsp6sw.mbn";
};
&remoteproc_wpss { &remoteproc_wpss {
status = "okay"; status = "okay";
firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";

37
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
View file

@ -87,6 +87,36 @@ &nvme_pwren {
pins = "gpio51"; pins = "gpio51";
}; };
&sound {
audio-routing =
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"VA DMIC3", "MIC BIAS3",
"TX SWR_ADC0", "ADC1_OUTPUT",
"TX SWR_ADC1", "ADC2_OUTPUT",
"TX SWR_ADC2", "ADC3_OUTPUT",
"TX SWR_DMIC0", "DMIC1_OUTPUT",
"TX SWR_DMIC1", "DMIC2_OUTPUT",
"TX SWR_DMIC2", "DMIC3_OUTPUT",
"TX SWR_DMIC3", "DMIC4_OUTPUT",
"TX SWR_DMIC4", "DMIC5_OUTPUT",
"TX SWR_DMIC5", "DMIC6_OUTPUT",
"TX SWR_DMIC6", "DMIC7_OUTPUT",
"TX SWR_DMIC7", "DMIC8_OUTPUT";
};
&wcd9385 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
};
&tlmm { &tlmm {
tp_int_odl: tp-int-odl { tp_int_odl: tp-int-odl {
pins = "gpio7"; pins = "gpio7";
@ -105,4 +135,11 @@ ts_reset_l: ts-reset-l {
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
}; };
us_euro_hs_sel: us-euro-hs-sel {
pins = "gpio81";
function = "gpio";
bias-pull-down;
drive-strength = <2>;
};
}; };

155
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
View file

@ -5,6 +5,161 @@
* Copyright (c) 2022, The Linux Foundation. All rights reserved. * Copyright (c) 2022, The Linux Foundation. All rights reserved.
*/ */
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */
sound: sound {
compatible = "google,sc7280-herobrine";
model = "sc7280-wcd938x-max98360a-1mic";
audio-routing =
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"VA DMIC3", "MIC BIAS3",
"TX SWR_ADC0", "ADC1_OUTPUT",
"TX SWR_ADC1", "ADC2_OUTPUT",
"TX SWR_ADC2", "ADC3_OUTPUT",
"TX SWR_DMIC0", "DMIC1_OUTPUT",
"TX SWR_DMIC1", "DMIC2_OUTPUT",
"TX SWR_DMIC2", "DMIC3_OUTPUT",
"TX SWR_DMIC3", "DMIC4_OUTPUT",
"TX SWR_DMIC4", "DMIC5_OUTPUT",
"TX SWR_DMIC5", "DMIC6_OUTPUT",
"TX SWR_DMIC6", "DMIC7_OUTPUT",
"TX SWR_DMIC7", "DMIC8_OUTPUT";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <0>;
dai-link@0 {
link-name = "MAX98360A";
reg = <0>;
cpu {
sound-dai = <&lpass_cpu MI2S_SECONDARY>;
};
codec {
sound-dai = <&max98360a>;
};
};
dai-link@1 {
link-name = "DisplayPort";
reg = <1>;
cpu {
sound-dai = <&lpass_cpu LPASS_DP_RX>;
};
codec {
sound-dai = <&mdss_dp>;
};
};
dai-link@2 {
link-name = "WCD9385 Playback";
reg = <2>;
cpu {
sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
};
codec {
sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>;
};
};
dai-link@3 {
link-name = "WCD9385 Capture";
reg = <3>;
cpu {
sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
};
codec {
sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>;
};
};
dai-link@4 {
link-name = "DMIC";
reg = <4>;
cpu {
sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
};
codec {
sound-dai = <&lpass_va_macro 0>;
};
};
};
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&lpass_cpu {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
dai-link@1 {
reg = <MI2S_SECONDARY>;
qcom,playback-sd-lines = <0>;
};
dai-link@5 {
reg = <LPASS_DP_RX>;
};
dai-link@6 {
reg = <LPASS_CDC_DMA_RX0>;
};
dai-link@19 {
reg = <LPASS_CDC_DMA_TX3>;
};
dai-link@25 {
reg = <LPASS_CDC_DMA_VA_TX0>;
};
};
&lpass_rx_macro {
status = "okay";
};
&lpass_tx_macro {
status = "okay";
};
&lpass_va_macro {
status = "okay";
};
&swr0 {
status = "okay";
};
&swr1 {
status = "okay";
};
&wcd9385 {
status = "okay";
};
/* PINCTRL */ /* PINCTRL */
&lpass_dmic01_clk { &lpass_dmic01_clk {

7
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
View file

@ -9,10 +9,11 @@
#include "sc7280-herobrine.dtsi" #include "sc7280-herobrine.dtsi"
#include "sc7280-herobrine-audio-wcd9385.dtsi" #include "sc7280-herobrine-audio-wcd9385.dtsi"
#include "sc7280-herobrine-lte-sku.dtsi"
/ { / {
model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
compatible = "google,hoglin", "qcom,sc7280"; compatible = "google,zoglin", "google,hoglin", "qcom,sc7280";
/* FIXED REGULATORS */ /* FIXED REGULATORS */
@ -167,7 +168,7 @@ &pm8350c_gpios {
"PMIC_EDP_BL_PWM", "PMIC_EDP_BL_PWM",
""; "";
edp_bl_reg_en: edp-bl-reg-en { edp_bl_reg_en: edp-bl-reg-en-state {
pins = "gpio6"; pins = "gpio6";
function = "normal"; function = "normal";
bias-disable; bias-disable;
@ -371,7 +372,5 @@ &tlmm {
"", /* 170 */ "", /* 170 */
"MOS_BLE_UART_TX", "MOS_BLE_UART_TX",
"MOS_BLE_UART_RX", "MOS_BLE_UART_RX",
"",
"",
""; "";
}; };

333
arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts Normal file
View file

@ -0,0 +1,333 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Evoker board device tree source
*
* Copyright 2022 Google LLC.
*/
/dts-v1/;
#include "sc7280-herobrine.dtsi"
/ {
model = "Google Evoker";
compatible = "google,evoker", "qcom,sc7280";
};
/*
* ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
*
* Sort order matches the order in the parent files (parents before children).
*/
&pp3300_codec {
status = "okay";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
hid-descr-addr = <0x20>;
vcc-supply = <&pp3300_z1>;
wakeup-source;
};
};
ts_i2c: &i2c13 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@10 {
compatible = "elan,ekth6915";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
interrupt-parent = <&tlmm>;
interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
vcc33-supply = <&ts_avdd>;
};
};
&ap_sar_sensor_i2c {
status = "okay";
};
&ap_sar_sensor0 {
status = "okay";
};
&ap_sar_sensor1 {
status = "okay";
};
&mdss_edp {
status = "okay";
};
&mdss_edp_phy {
status = "okay";
};
/* For nvme */
&pcie1 {
status = "okay";
};
/* For nvme */
&pcie1_phy {
status = "okay";
};
&pwmleds {
status = "okay";
};
/* For eMMC */
&sdhc_1 {
status = "okay";
};
/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
&ts_rst_conn {
bias-disable;
};
/* PINCTRL - BOARD-SPECIFIC */
/*
* Methodology for gpio-line-names:
* - If a pin goes to herobrine board and is named it gets that name.
* - If a pin goes to herobrine board and is not named, it gets no name.
* - If a pin is totally internal to Qcard then it gets Qcard name.
* - If a pin is not hooked up on Qcard, it gets no name.
*/
&pm8350c_gpios {
gpio-line-names = "FLASH_STROBE_1", /* 1 */
"AP_SUSPEND",
"PM8008_1_RST_N",
"",
"",
"",
"PMIC_EDP_BL_EN",
"PMIC_EDP_BL_PWM",
"";
};
&tlmm {
gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
"AP_TP_I2C_SCL",
"SSD_RST_L",
"PE_WAKE_ODL",
"AP_SAR_SDA",
"AP_SAR_SCL",
"PRB_SC_GPIO_6",
"TP_INT_ODL",
"HP_I2C_SDA",
"HP_I2C_SCL",
"GNSS_L1_EN", /* 10 */
"GNSS_L5_EN",
"SPI_AP_MOSI",
"SPI_AP_MISO",
"SPI_AP_CLK",
"SPI_AP_CS0_L",
/*
* AP_FLASH_WP is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_OD.
*/
"AP_FLASH_WP",
"",
"AP_EC_INT_L",
"",
"UF_CAM_RST_L", /* 20 */
"WF_CAM_RST_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"PM8008_IRQ_1",
"HOST2WLAN_SOL",
"WLAN2HOST_SOL",
"MOS_BT_UART_CTS",
"MOS_BT_UART_RFR",
"MOS_BT_UART_TX", /* 30 */
"MOS_BT_UART_RX",
"PRB_SC_GPIO_32",
"HUB_RST_L",
"",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_EC_SPI_MISO", /* 40 */
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"LCM_RST_L",
"EARLY_EUD_N",
"",
"DP_HOT_PLUG_DET",
"IO_BRD_MLB_ID0",
"IO_BRD_MLB_ID1",
"IO_BRD_MLB_ID2", /* 50 */
"SSD_EN",
"TS_I2C_SDA_CONN",
"TS_I2C_CLK_CONN",
"TS_RST_CONN",
"TS_INT_CONN",
"AP_I2C_TPM_SDA",
"AP_I2C_TPM_SCL",
"PRB_SC_GPIO_58",
"PRB_SC_GPIO_59",
"EDP_HOT_PLUG_DET_N", /* 60 */
"FP_TO_AP_IRQ_L",
"",
"AMP_EN",
"CAM0_MCLK_GPIO_64",
"CAM1_MCLK_GPIO_65",
"WF_CAM_MCLK",
"PRB_SC_GPIO_67",
"FPMCU_BOOT0",
"UF_CAM_SDA",
"UF_CAM_SCL", /* 70 */
"",
"",
"WF_CAM_SDA",
"WF_CAM_SCL",
"",
"",
"EN_FP_RAILS",
"FP_RST_L",
"PCIE1_CLKREQ_ODL",
"EN_PP3300_DX_EDP", /* 80 */
"SC_GPIO_81",
"FORCED_USB_BOOT",
"WCD_RESET_N",
"MOS_WLAN_EN",
"MOS_BT_EN",
"MOS_SW_CTRL",
"MOS_PCIE0_RST",
"MOS_PCIE0_CLKREQ_N",
"MOS_PCIE0_WAKE_N",
"MOS_LAA_AS_EN", /* 90 */
"SD_CD_ODL",
"",
"",
"MOS_BT_WLAN_SLIMBUS_CLK",
"MOS_BT_WLAN_SLIMBUS_DAT0",
"HP_MCLK",
"HP_BCLK",
"HP_DOUT",
"HP_DIN",
"HP_LRCLK", /* 100 */
"HP_IRQ",
"",
"",
"GSC_AP_INT_ODL",
"EN_PP3300_CODEC",
"AMP_BCLK",
"AMP_DIN",
"AMP_LRCLK",
"UIM1_DATA_GPIO_109",
"UIM1_CLK_GPIO_110", /* 110 */
"UIM1_RESET_GPIO_111",
"PRB_SC_GPIO_112",
"UIM0_DATA",
"UIM0_CLK",
"UIM0_RST",
"UIM0_PRESENT_ODL",
"SDM_RFFE0_CLK",
"SDM_RFFE0_DATA",
"WF_CAM_EN",
"FASTBOOT_SEL_0", /* 120 */
"SC_GPIO_121",
"FASTBOOT_SEL_1",
"SC_GPIO_123",
"FASTBOOT_SEL_2",
"SM_RFFE4_CLK_GRFC_8",
"SM_RFFE4_DATA_GRFC_9",
"WLAN_COEX_UART1_RX",
"WLAN_COEX_UART1_TX",
"PRB_SC_GPIO_129",
"LCM_ID0", /* 130 */
"LCM_ID1",
"",
"SDR_QLINK_REQ",
"SDR_QLINK_EN",
"QLINK0_WMSS_RESET_N",
"SMR526_QLINK1_REQ",
"SMR526_QLINK1_EN",
"SMR526_QLINK1_WMSS_RESET_N",
"PRB_SC_GPIO_139",
"SAR1_IRQ_ODL", /* 140 */
"SAR0_IRQ_ODL",
"PRB_SC_GPIO_142",
"",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0",
"WCD_SWR_RX_DATA1",
"DMIC01_CLK", /* 150 */
"DMIC01_DATA",
"DMIC23_CLK",
"DMIC23_DATA",
"",
"",
"EC_IN_RW_ODL",
"HUB_EN",
"WCD_SWR_TX_DATA2",
"",
"", /* 160 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
"",
"";
};

1
arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
View file

@ -8,6 +8,7 @@
/dts-v1/; /dts-v1/;
#include "sc7280-herobrine.dtsi" #include "sc7280-herobrine.dtsi"
#include "sc7280-herobrine-lte-sku.dtsi"
/ { / {
model = "Google Herobrine (rev1+)"; model = "Google Herobrine (rev1+)";

17
arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Herobrine dts fragment for LTE SKUs
*
* Copyright 2022 Google LLC.
*/
/* Modem setup is different on Chrome setups than typical Qualcomm setup */
&remoteproc_mpss {
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&mba_mem>, <&mpss_mem>;
firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn",
"qcom/sc7280-herobrine/modem/qdsp6sw.mbn";
status = "okay";
};

325
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts
View file

@ -7,327 +7,10 @@
/dts-v1/; /dts-v1/;
#include "sc7280-herobrine.dtsi" #include "sc7280-herobrine-villager.dtsi"
#include "sc7280-herobrine-lte-sku.dtsi"
/ { / {
model = "Google Villager (rev0+)"; model = "Google Villager (rev0)";
compatible = "google,villager", "qcom,sc7280"; compatible = "google,villager-rev0", "qcom,sc7280";
};
/*
* ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
*
* Sort order matches the order in the parent files (parents before children).
*/
&pp3300_codec {
status = "okay";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
hid-descr-addr = <0x20>;
vcc-supply = <&pp3300_z1>;
wakeup-source;
};
};
ts_i2c: &i2c13 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@10 {
compatible = "elan,ekth6915";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
interrupt-parent = <&tlmm>;
interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
vcc33-supply = <&ts_avdd>;
};
};
&ap_sar_sensor_i2c {
status = "okay";
};
&ap_sar_sensor0 {
status = "okay";
};
&ap_sar_sensor1 {
status = "okay";
};
&mdss_edp {
status = "okay";
};
&mdss_edp_phy {
status = "okay";
};
/* For nvme */
&pcie1 {
status = "okay";
};
/* For nvme */
&pcie1_phy {
status = "okay";
};
&pwmleds {
status = "okay";
};
/* For eMMC */
&sdhc_1 {
status = "okay";
};
/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
&ts_rst_conn {
bias-disable;
};
/* PINCTRL - BOARD-SPECIFIC */
/*
* Methodology for gpio-line-names:
* - If a pin goes to herobrine board and is named it gets that name.
* - If a pin goes to herobrine board and is not named, it gets no name.
* - If a pin is totally internal to Qcard then it gets Qcard name.
* - If a pin is not hooked up on Qcard, it gets no name.
*/
&pm8350c_gpios {
gpio-line-names = "FLASH_STROBE_1", /* 1 */
"AP_SUSPEND",
"PM8008_1_RST_N",
"",
"",
"",
"PMIC_EDP_BL_EN",
"PMIC_EDP_BL_PWM",
"";
};
&tlmm {
gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
"AP_TP_I2C_SCL",
"SSD_RST_L",
"PE_WAKE_ODL",
"AP_SAR_SDA",
"AP_SAR_SCL",
"PRB_SC_GPIO_6",
"TP_INT_ODL",
"HP_I2C_SDA",
"HP_I2C_SCL",
"GNSS_L1_EN", /* 10 */
"GNSS_L5_EN",
"SPI_AP_MOSI",
"SPI_AP_MISO",
"SPI_AP_CLK",
"SPI_AP_CS0_L",
/*
* AP_FLASH_WP is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_OD.
*/
"AP_FLASH_WP",
"",
"AP_EC_INT_L",
"",
"UF_CAM_RST_L", /* 20 */
"WF_CAM_RST_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"PM8008_IRQ_1",
"HOST2WLAN_SOL",
"WLAN2HOST_SOL",
"MOS_BT_UART_CTS",
"MOS_BT_UART_RFR",
"MOS_BT_UART_TX", /* 30 */
"MOS_BT_UART_RX",
"PRB_SC_GPIO_32",
"HUB_RST_L",
"",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_EC_SPI_MISO", /* 40 */
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"LCM_RST_L",
"EARLY_EUD_N",
"",
"DP_HOT_PLUG_DET",
"IO_BRD_MLB_ID0",
"IO_BRD_MLB_ID1",
"IO_BRD_MLB_ID2", /* 50 */
"SSD_EN",
"TS_I2C_SDA_CONN",
"TS_I2C_CLK_CONN",
"TS_RST_CONN",
"TS_INT_CONN",
"AP_I2C_TPM_SDA",
"AP_I2C_TPM_SCL",
"PRB_SC_GPIO_58",
"PRB_SC_GPIO_59",
"EDP_HOT_PLUG_DET_N", /* 60 */
"FP_TO_AP_IRQ_L",
"",
"AMP_EN",
"CAM0_MCLK_GPIO_64",
"CAM1_MCLK_GPIO_65",
"WF_CAM_MCLK",
"PRB_SC_GPIO_67",
"FPMCU_BOOT0",
"UF_CAM_SDA",
"UF_CAM_SCL", /* 70 */
"",
"",
"WF_CAM_SDA",
"WF_CAM_SCL",
"",
"",
"EN_FP_RAILS",
"FP_RST_L",
"PCIE1_CLKREQ_ODL",
"EN_PP3300_DX_EDP", /* 80 */
"SC_GPIO_81",
"FORCED_USB_BOOT",
"WCD_RESET_N",
"MOS_WLAN_EN",
"MOS_BT_EN",
"MOS_SW_CTRL",
"MOS_PCIE0_RST",
"MOS_PCIE0_CLKREQ_N",
"MOS_PCIE0_WAKE_N",
"MOS_LAA_AS_EN", /* 90 */
"SD_CD_ODL",
"",
"",
"MOS_BT_WLAN_SLIMBUS_CLK",
"MOS_BT_WLAN_SLIMBUS_DAT0",
"HP_MCLK",
"HP_BCLK",
"HP_DOUT",
"HP_DIN",
"HP_LRCLK", /* 100 */
"HP_IRQ",
"",
"",
"GSC_AP_INT_ODL",
"EN_PP3300_CODEC",
"AMP_BCLK",
"AMP_DIN",
"AMP_LRCLK",
"UIM1_DATA_GPIO_109",
"UIM1_CLK_GPIO_110", /* 110 */
"UIM1_RESET_GPIO_111",
"PRB_SC_GPIO_112",
"UIM0_DATA",
"UIM0_CLK",
"UIM0_RST",
"UIM0_PRESENT_ODL",
"SDM_RFFE0_CLK",
"SDM_RFFE0_DATA",
"WF_CAM_EN",
"FASTBOOT_SEL_0", /* 120 */
"SC_GPIO_121",
"FASTBOOT_SEL_1",
"SC_GPIO_123",
"FASTBOOT_SEL_2",
"SM_RFFE4_CLK_GRFC_8",
"SM_RFFE4_DATA_GRFC_9",
"WLAN_COEX_UART1_RX",
"WLAN_COEX_UART1_TX",
"PRB_SC_GPIO_129",
"LCM_ID0", /* 130 */
"LCM_ID1",
"",
"SDR_QLINK_REQ",
"SDR_QLINK_EN",
"QLINK0_WMSS_RESET_N",
"SMR526_QLINK1_REQ",
"SMR526_QLINK1_EN",
"SMR526_QLINK1_WMSS_RESET_N",
"PRB_SC_GPIO_139",
"SAR1_IRQ_ODL", /* 140 */
"SAR0_IRQ_ODL",
"PRB_SC_GPIO_142",
"",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0",
"WCD_SWR_RX_DATA1",
"DMIC01_CLK", /* 150 */
"DMIC01_DATA",
"DMIC23_CLK",
"DMIC23_DATA",
"",
"",
"EC_IN_RW_ODL",
"HUB_EN",
"WCD_SWR_TX_DATA2",
"",
"", /* 160 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
"",
"";
}; };

14
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Villager board device tree source
*
* Copyright 2022 Google LLC.
*/
#include "sc7280-herobrine-villager-r1.dts"
#include "sc7280-herobrine-lte-sku.dtsi"
/ {
model = "Google Villager (rev1+) with LTE";
compatible = "google,villager-sku512", "qcom,sc7280";
};

43
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Villager board device tree source
*
* Copyright 2022 Google LLC.
*/
/dts-v1/;
#include "sc7280-herobrine-villager.dtsi"
#include "sc7280-herobrine-audio-wcd9385.dtsi"
/ {
model = "Google Villager (rev1+)";
compatible = "google,villager", "qcom,sc7280";
};
&lpass_va_macro {
vdd-micb-supply = <&pp1800_l2c>;
};
&sound {
audio-routing =
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"VA DMIC2", "vdd-micb",
"VA DMIC3", "vdd-micb",
"TX SWR_ADC0", "ADC1_OUTPUT",
"TX SWR_ADC1", "ADC2_OUTPUT",
"TX SWR_ADC2", "ADC3_OUTPUT",
"TX SWR_DMIC0", "DMIC1_OUTPUT",
"TX SWR_DMIC1", "DMIC2_OUTPUT",
"TX SWR_DMIC2", "DMIC3_OUTPUT",
"TX SWR_DMIC3", "DMIC4_OUTPUT",
"TX SWR_DMIC4", "DMIC5_OUTPUT",
"TX SWR_DMIC5", "DMIC6_OUTPUT",
"TX SWR_DMIC6", "DMIC7_OUTPUT",
"TX SWR_DMIC7", "DMIC8_OUTPUT";
};

326
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi Normal file
View file

@ -0,0 +1,326 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Villager board device tree source
*
* Copyright 2022 Google LLC.
*/
#include "sc7280-herobrine.dtsi"
/*
* ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
*
* Sort order matches the order in the parent files (parents before children).
*/
&pp3300_codec {
status = "okay";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
hid-descr-addr = <0x20>;
vcc-supply = <&pp3300_z1>;
wakeup-source;
};
};
ts_i2c: &i2c13 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@10 {
compatible = "elan,ekth6915";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
interrupt-parent = <&tlmm>;
interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
vcc33-supply = <&ts_avdd>;
};
};
&ap_sar_sensor_i2c {
status = "okay";
};
&ap_sar_sensor0 {
status = "okay";
};
&ap_sar_sensor1 {
status = "okay";
};
&mdss_edp {
status = "okay";
};
&mdss_edp_phy {
status = "okay";
};
/* For nvme */
&pcie1 {
status = "okay";
};
/* For nvme */
&pcie1_phy {
status = "okay";
};
&pwmleds {
status = "okay";
};
/* For eMMC */
&sdhc_1 {
status = "okay";
};
/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
&ts_rst_conn {
bias-disable;
};
/* PINCTRL - BOARD-SPECIFIC */
/*
* Methodology for gpio-line-names:
* - If a pin goes to herobrine board and is named it gets that name.
* - If a pin goes to herobrine board and is not named, it gets no name.
* - If a pin is totally internal to Qcard then it gets Qcard name.
* - If a pin is not hooked up on Qcard, it gets no name.
*/
&pm8350c_gpios {
gpio-line-names = "FLASH_STROBE_1", /* 1 */
"AP_SUSPEND",
"PM8008_1_RST_N",
"",
"",
"",
"PMIC_EDP_BL_EN",
"PMIC_EDP_BL_PWM",
"";
};
&tlmm {
gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
"AP_TP_I2C_SCL",
"SSD_RST_L",
"PE_WAKE_ODL",
"AP_SAR_SDA",
"AP_SAR_SCL",
"PRB_SC_GPIO_6",
"TP_INT_ODL",
"HP_I2C_SDA",
"HP_I2C_SCL",
"GNSS_L1_EN", /* 10 */
"GNSS_L5_EN",
"SPI_AP_MOSI",
"SPI_AP_MISO",
"SPI_AP_CLK",
"SPI_AP_CS0_L",
/*
* AP_FLASH_WP is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_OD.
*/
"AP_FLASH_WP",
"",
"AP_EC_INT_L",
"",
"UF_CAM_RST_L", /* 20 */
"WF_CAM_RST_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"PM8008_IRQ_1",
"HOST2WLAN_SOL",
"WLAN2HOST_SOL",
"MOS_BT_UART_CTS",
"MOS_BT_UART_RFR",
"MOS_BT_UART_TX", /* 30 */
"MOS_BT_UART_RX",
"PRB_SC_GPIO_32",
"HUB_RST_L",
"",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_EC_SPI_MISO", /* 40 */
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"LCM_RST_L",
"EARLY_EUD_N",
"",
"DP_HOT_PLUG_DET",
"IO_BRD_MLB_ID0",
"IO_BRD_MLB_ID1",
"IO_BRD_MLB_ID2", /* 50 */
"SSD_EN",
"TS_I2C_SDA_CONN",
"TS_I2C_CLK_CONN",
"TS_RST_CONN",
"TS_INT_CONN",
"AP_I2C_TPM_SDA",
"AP_I2C_TPM_SCL",
"PRB_SC_GPIO_58",
"PRB_SC_GPIO_59",
"EDP_HOT_PLUG_DET_N", /* 60 */
"FP_TO_AP_IRQ_L",
"",
"AMP_EN",
"CAM0_MCLK_GPIO_64",
"CAM1_MCLK_GPIO_65",
"WF_CAM_MCLK",
"PRB_SC_GPIO_67",
"FPMCU_BOOT0",
"UF_CAM_SDA",
"UF_CAM_SCL", /* 70 */
"",
"",
"WF_CAM_SDA",
"WF_CAM_SCL",
"",
"",
"EN_FP_RAILS",
"FP_RST_L",
"PCIE1_CLKREQ_ODL",
"EN_PP3300_DX_EDP", /* 80 */
"SC_GPIO_81",
"FORCED_USB_BOOT",
"WCD_RESET_N",
"MOS_WLAN_EN",
"MOS_BT_EN",
"MOS_SW_CTRL",
"MOS_PCIE0_RST",
"MOS_PCIE0_CLKREQ_N",
"MOS_PCIE0_WAKE_N",
"MOS_LAA_AS_EN", /* 90 */
"SD_CD_ODL",
"",
"",
"MOS_BT_WLAN_SLIMBUS_CLK",
"MOS_BT_WLAN_SLIMBUS_DAT0",
"HP_MCLK",
"HP_BCLK",
"HP_DOUT",
"HP_DIN",
"HP_LRCLK", /* 100 */
"HP_IRQ",
"",
"",
"GSC_AP_INT_ODL",
"EN_PP3300_CODEC",
"AMP_BCLK",
"AMP_DIN",
"AMP_LRCLK",
"UIM1_DATA_GPIO_109",
"UIM1_CLK_GPIO_110", /* 110 */
"UIM1_RESET_GPIO_111",
"PRB_SC_GPIO_112",
"UIM0_DATA",
"UIM0_CLK",
"UIM0_RST",
"UIM0_PRESENT_ODL",
"SDM_RFFE0_CLK",
"SDM_RFFE0_DATA",
"WF_CAM_EN",
"FASTBOOT_SEL_0", /* 120 */
"SC_GPIO_121",
"FASTBOOT_SEL_1",
"SC_GPIO_123",
"FASTBOOT_SEL_2",
"SM_RFFE4_CLK_GRFC_8",
"SM_RFFE4_DATA_GRFC_9",
"WLAN_COEX_UART1_RX",
"WLAN_COEX_UART1_TX",
"PRB_SC_GPIO_129",
"LCM_ID0", /* 130 */
"LCM_ID1",
"",
"SDR_QLINK_REQ",
"SDR_QLINK_EN",
"QLINK0_WMSS_RESET_N",
"SMR526_QLINK1_REQ",
"SMR526_QLINK1_EN",
"SMR526_QLINK1_WMSS_RESET_N",
"PRB_SC_GPIO_139",
"SAR1_IRQ_ODL", /* 140 */
"SAR0_IRQ_ODL",
"PRB_SC_GPIO_142",
"",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0",
"WCD_SWR_RX_DATA1",
"DMIC01_CLK", /* 150 */
"DMIC01_DATA",
"DMIC23_CLK",
"DMIC23_DATA",
"",
"",
"EC_IN_RW_ODL",
"HUB_EN",
"WCD_SWR_TX_DATA2",
"",
"", /* 160 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
"",
"";
};

87
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View file

@ -144,8 +144,8 @@ pp3300_hub: pp3300-hub-regulator {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
/* The BIOS leaves this regulator on */
regulator-boot-on; regulator-boot-on;
regulator-always-on;
gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>; gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
@ -296,6 +296,14 @@ pp1200_wf_cam: pp1200-wf-cam-regulator {
/* BOARD-SPECIFIC TOP LEVEL NODES */ /* BOARD-SPECIFIC TOP LEVEL NODES */
max98360a: audio-codec-0 {
compatible = "maxim,max98360a";
pinctrl-names = "default";
pinctrl-0 = <&amp_en>;
sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
pwmleds: pwmleds { pwmleds: pwmleds {
compatible = "pwm-leds"; compatible = "pwm-leds";
status = "disabled"; status = "disabled";
@ -446,7 +454,7 @@ &pcie1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;
perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&pp3300_ssd>; vddpe-3v3-supply = <&pp3300_ssd>;
}; };
@ -596,6 +604,25 @@ &usb_1 {
&usb_1_dwc3 { &usb_1_dwc3 {
dr_mode = "host"; dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
/* 2.x hub on port 1 */
usb_hub_2_x: hub@1 {
compatible = "usbbda,5411";
reg = <1>;
vdd-supply = <&pp3300_hub>;
peer-hub = <&usb_hub_3_x>;
};
/* 3.x hub on port 2 */
usb_hub_3_x: hub@2 {
compatible = "usbbda,411";
reg = <2>;
vdd-supply = <&pp3300_hub>;
peer-hub = <&usb_hub_2_x>;
};
}; };
&usb_1_hsphy { &usb_1_hsphy {
@ -606,18 +633,6 @@ &usb_1_qmpphy {
status = "okay"; status = "okay";
}; };
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&usb_2_hsphy {
status = "okay";
};
/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
&dp_hot_plug_det { &dp_hot_plug_det {
@ -729,27 +744,27 @@ &tlmm {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&bios_flash_wp_od>; pinctrl-0 = <&bios_flash_wp_od>;
amp_en: amp-en { amp_en: amp-en-pins {
pins = "gpio63"; pins = "gpio63";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
drive-strength = <2>; drive-strength = <2>;
}; };
ap_ec_int_l: ap-ec-int-l { ap_ec_int_l: ap-ec-int-l-pins {
pins = "gpio18"; pins = "gpio18";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
bios_flash_wp_od: bios-flash-wp-od { bios_flash_wp_od: bios-flash-wp-od-pins {
pins = "gpio16"; pins = "gpio16";
function = "gpio"; function = "gpio";
/* Has external pull */ /* Has external pull */
bias-disable; bias-disable;
}; };
en_fp_rails: en-fp-rails { en_fp_rails: en-fp-rails-pins {
pins = "gpio77"; pins = "gpio77";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
@ -757,60 +772,60 @@ en_fp_rails: en-fp-rails {
output-high; output-high;
}; };
en_pp3300_codec: en-pp3300-codec { en_pp3300_codec: en-pp3300-codec-pins {
pins = "gpio105"; pins = "gpio105";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
drive-strength = <2>; drive-strength = <2>;
}; };
en_pp3300_dx_edp: en-pp3300-dx-edp { en_pp3300_dx_edp: en-pp3300-dx-edp-pins {
pins = "gpio80"; pins = "gpio80";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
drive-strength = <2>; drive-strength = <2>;
}; };
fp_rst_l: fp-rst-l { fp_rst_l: fp-rst-l-pins {
pins = "gpio78"; pins = "gpio78";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
drive-strength = <2>; drive-strength = <2>;
}; };
fp_to_ap_irq_l: fp-to-ap-irq-l { fp_to_ap_irq_l: fp-to-ap-irq-l-pins {
pins = "gpio61"; pins = "gpio61";
function = "gpio"; function = "gpio";
/* Has external pullup */ /* Has external pullup */
bias-disable; bias-disable;
}; };
fpmcu_boot0: fpmcu-boot0 { fpmcu_boot0: fpmcu-boot0-pins {
pins = "gpio68"; pins = "gpio68";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
}; };
gsc_ap_int_odl: gsc-ap-int-odl { gsc_ap_int_odl: gsc-ap-int-odl-pins {
pins = "gpio104"; pins = "gpio104";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
hp_irq: hp-irq { hp_irq: hp-irq-pins {
pins = "gpio101"; pins = "gpio101";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
hub_en: hub-en { hub_en: hub-en-pins {
pins = "gpio157"; pins = "gpio157";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
drive-strength = <2>; drive-strength = <2>;
}; };
pe_wake_odl: pe-wake-odl { pe_wake_odl: pe-wake-odl-pins {
pins = "gpio3"; pins = "gpio3";
function = "gpio"; function = "gpio";
/* Has external pull */ /* Has external pull */
@ -819,45 +834,45 @@ pe_wake_odl: pe-wake-odl {
}; };
/* For ap_spi_fp */ /* For ap_spi_fp */
qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high { qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-pins {
pins = "gpio39"; pins = "gpio39";
function = "gpio"; function = "gpio";
output-high; output-high;
}; };
/* For ap_ec_spi */ /* For ap_ec_spi */
qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins {
pins = "gpio43"; pins = "gpio43";
function = "gpio"; function = "gpio";
output-high; output-high;
}; };
sar0_irq_odl: sar0-irq-odl { sar0_irq_odl: sar0-irq-odl-pins {
pins = "gpio141"; pins = "gpio141";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
sar1_irq_odl: sar1-irq-odl { sar1_irq_odl: sar1-irq-odl-pins {
pins = "gpio140"; pins = "gpio140";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
sd_cd_odl: sd-cd-odl { sd_cd_odl: sd-cd-odl-pins {
pins = "gpio91"; pins = "gpio91";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
ssd_en: ssd-en { ssd_en: ssd-en-pins {
pins = "gpio51"; pins = "gpio51";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
drive-strength = <2>; drive-strength = <2>;
}; };
ssd_rst_l: ssd-rst-l { ssd_rst_l: ssd-rst-l-pins {
pins = "gpio2"; pins = "gpio2";
function = "gpio"; function = "gpio";
bias-disable; bias-disable;
@ -865,14 +880,14 @@ ssd_rst_l: ssd-rst-l {
output-low; output-low;
}; };
tp_int_odl: tp-int-odl { tp_int_odl: tp-int-odl-pins {
pins = "gpio7"; pins = "gpio7";
function = "gpio"; function = "gpio";
/* Has external pullup */ /* Has external pullup */
bias-disable; bias-disable;
}; };
wf_cam_en: wf-cam-en { wf_cam_en: wf-cam-en-pins {
pins = "gpio119"; pins = "gpio119";
function = "gpio"; function = "gpio";
/* Has external pulldown */ /* Has external pulldown */

8
arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
View file

@ -79,26 +79,26 @@ cr50: tpm@0 {
}; };
&tlmm { &tlmm {
ap_ec_int_l: ap-ec-int-l { ap_ec_int_l: ap-ec-int-l-pins {
pins = "gpio18"; pins = "gpio18";
function = "gpio"; function = "gpio";
input-enable; input-enable;
bias-pull-up; bias-pull-up;
}; };
h1_ap_int_odl: h1-ap-int-odl { h1_ap_int_odl: h1-ap-int-odl-pins {
pins = "gpio104"; pins = "gpio104";
function = "gpio"; function = "gpio";
input-enable; input-enable;
bias-pull-up; bias-pull-up;
}; };
qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins {
pins = "gpio43"; pins = "gpio43";
output-high; output-high;
}; };
qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high { qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-pins {
pins = "gpio59"; pins = "gpio59";
output-high; output-high;
}; };

3
arch/arm64/boot/dts/qcom/sc7280-idp.dts
View file

@ -10,6 +10,7 @@
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include "sc7280-idp.dtsi" #include "sc7280-idp.dtsi"
#include "pmr735a.dtsi" #include "pmr735a.dtsi"
#include "sc7280-herobrine-lte-sku.dtsi"
/ { / {
model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform"; model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform";
@ -78,7 +79,7 @@ &nvme_3v3_regulator {
}; };
&pmk8350_vadc { &pmk8350_vadc {
pmr735a_die_temp { pmr735a-die-temp@403 {
reg = <PMR735A_ADC7_DIE_TEMP>; reg = <PMR735A_ADC7_DIE_TEMP>;
label = "pmr735a_die_temp"; label = "pmr735a_die_temp";
qcom,pre-scaling = <1 1>; qcom,pre-scaling = <1 1>;

240
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View file

@ -20,6 +20,42 @@ aliases {
serial1 = &uart7; serial1 = &uart7;
}; };
max98360a: audio-codec-0 {
compatible = "maxim,max98360a";
pinctrl-names = "default";
pinctrl-0 = <&amp_en>;
sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
wcd9385: audio-codec-1 {
compatible = "qcom,wcd9385-codec";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&wcd_reset_n>;
pinctrl-1 = <&wcd_reset_n_sleep>;
reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
vdd-rxtx-supply = <&vreg_l18b_1p8>;
vdd-io-supply = <&vreg_l18b_1p8>;
vdd-buck-supply = <&vreg_l17b_1p8>;
vdd-mic-bias-supply = <&vreg_bob>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
#sound-dai-cells = <1>;
};
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
label = "gpio-keys"; label = "gpio-keys";
@ -49,6 +85,104 @@ nvme_3v3_regulator: nvme-3v3-regulator {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&nvme_pwren>; pinctrl-0 = <&nvme_pwren>;
}; };
sound: sound {
compatible = "google,sc7280-herobrine";
model = "sc7280-wcd938x-max98360a-1mic";
audio-routing =
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "MIC BIAS3",
"VA DMIC1", "MIC BIAS3",
"VA DMIC2", "MIC BIAS1",
"VA DMIC3", "MIC BIAS1",
"TX SWR_ADC0", "ADC1_OUTPUT",
"TX SWR_ADC1", "ADC2_OUTPUT",
"TX SWR_ADC2", "ADC3_OUTPUT",
"TX SWR_DMIC0", "DMIC1_OUTPUT",
"TX SWR_DMIC1", "DMIC2_OUTPUT",
"TX SWR_DMIC2", "DMIC3_OUTPUT",
"TX SWR_DMIC3", "DMIC4_OUTPUT",
"TX SWR_DMIC4", "DMIC5_OUTPUT",
"TX SWR_DMIC5", "DMIC6_OUTPUT",
"TX SWR_DMIC6", "DMIC7_OUTPUT",
"TX SWR_DMIC7", "DMIC8_OUTPUT";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <0>;
dai-link@0 {
link-name = "MAX98360A";
reg = <0>;
cpu {
sound-dai = <&lpass_cpu MI2S_SECONDARY>;
};
codec {
sound-dai = <&max98360a>;
};
};
dai-link@1 {
link-name = "DisplayPort";
reg = <1>;
cpu {
sound-dai = <&lpass_cpu LPASS_DP_RX>;
};
codec {
sound-dai = <&mdss_dp>;
};
};
dai-link@2 {
link-name = "WCD9385 Playback";
reg = <2>;
cpu {
sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
};
codec {
sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>;
};
};
dai-link@3 {
link-name = "WCD9385 Capture";
reg = <3>;
cpu {
sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
};
codec {
sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>;
};
};
dai-link@4 {
link-name = "DMIC";
reg = <4>;
cpu {
sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
};
codec {
sound-dai = <&lpass_va_macro 0>;
};
};
};
}; };
&apps_rsc { &apps_rsc {
@ -246,9 +380,50 @@ &ipa {
modem-init; modem-init;
}; };
&lpass_cpu {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
dai-link@1 {
reg = <MI2S_SECONDARY>;
qcom,playback-sd-lines = <0>;
};
dai-link@5 {
reg = <LPASS_DP_RX>;
};
dai-link@6 {
reg = <LPASS_CDC_DMA_RX0>;
};
dai-link@19 {
reg = <LPASS_CDC_DMA_TX3>;
};
dai-link@25 {
reg = <LPASS_CDC_DMA_VA_TX0>;
};
};
&lpass_rx_macro {
status = "okay";
};
&lpass_tx_macro {
status = "okay";
};
&lpass_va_macro {
status = "okay";
vdd-micb-supply = <&vreg_bob>;
};
&pcie1 { &pcie1 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>; vddpe-3v3-supply = <&nvme_3v3_regulator>;
@ -264,7 +439,7 @@ &pcie1_phy {
}; };
&pmk8350_vadc { &pmk8350_vadc {
pmk8350_die_temp { pmk8350-die-temp@3 {
reg = <PMK8350_ADC7_DIE_TEMP>; reg = <PMK8350_ADC7_DIE_TEMP>;
label = "pmk8350_die_temp"; label = "pmk8350_die_temp";
qcom,pre-scaling = <1 1>; qcom,pre-scaling = <1 1>;
@ -306,6 +481,28 @@ &sdhc_2 {
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
}; };
&swr0 {
status = "okay";
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
#sound-dai-cells = <1>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
&swr1 {
status = "okay";
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
#sound-dai-cells = <1>;
qcom,tx-port-mapping = <1 2 3 4>;
};
};
&uart5 { &uart5 {
compatible = "qcom,geni-debug-uart"; compatible = "qcom,geni-debug-uart";
status = "okay"; status = "okay";
@ -550,18 +747,24 @@ &sdc2_data {
}; };
&tlmm { &tlmm {
bt_en: bt-en { amp_en: amp-en {
pins = "gpio63";
bias-pull-down;
drive-strength = <2>;
};
bt_en: bt-en-pins {
pins = "gpio85"; pins = "gpio85";
function = "gpio"; function = "gpio";
output-low; output-low;
bias-disable; bias-disable;
}; };
nvme_pwren: nvme-pwren { nvme_pwren: nvme-pwren-pins {
function = "gpio"; function = "gpio";
}; };
pcie1_reset_n: pcie1-reset-n { pcie1_reset_n: pcie1-reset-n-pins {
pins = "gpio2"; pins = "gpio2";
function = "gpio"; function = "gpio";
@ -570,7 +773,7 @@ pcie1_reset_n: pcie1-reset-n {
bias-disable; bias-disable;
}; };
pcie1_wake_n: pcie1-wake-n { pcie1_wake_n: pcie1-wake-n-pins {
pins = "gpio3"; pins = "gpio3";
function = "gpio"; function = "gpio";
@ -578,7 +781,7 @@ pcie1_wake_n: pcie1-wake-n {
bias-pull-up; bias-pull-up;
}; };
qup_uart7_sleep_cts: qup-uart7-sleep-cts { qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins {
pins = "gpio28"; pins = "gpio28";
function = "gpio"; function = "gpio";
/* /*
@ -591,7 +794,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
bias-bus-hold; bias-bus-hold;
}; };
qup_uart7_sleep_rts: qup-uart7-sleep-rts { qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins {
pins = "gpio29"; pins = "gpio29";
function = "gpio"; function = "gpio";
/* /*
@ -603,7 +806,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts {
bias-pull-down; bias-pull-down;
}; };
qup_uart7_sleep_tx: qup-uart7-sleep-tx { qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins {
pins = "gpio30"; pins = "gpio30";
function = "gpio"; function = "gpio";
/* /*
@ -613,7 +816,7 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx {
bias-pull-up; bias-pull-up;
}; };
qup_uart7_sleep_rx: qup-uart7-sleep-rx { qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins {
pins = "gpio31"; pins = "gpio31";
function = "gpio"; function = "gpio";
/* /*
@ -624,15 +827,28 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
bias-pull-up; bias-pull-up;
}; };
sd_cd: sd-cd { sd_cd: sd-cd-pins {
pins = "gpio91"; pins = "gpio91";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
sw_ctrl: sw-ctrl { sw_ctrl: sw-ctrl-pins {
pins = "gpio86"; pins = "gpio86";
function = "gpio"; function = "gpio";
bias-pull-down; bias-pull-down;
}; };
wcd_reset_n: wcd-reset-n {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
};
wcd_reset_n_sleep: wcd-reset-n-sleep {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
}; };

88
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View file

@ -28,6 +28,38 @@ aliases {
bluetooth0 = &bluetooth; bluetooth0 = &bluetooth;
serial0 = &uart5; serial0 = &uart5;
serial1 = &uart7; serial1 = &uart7;
wifi0 = &wifi;
};
wcd9385: audio-codec-1 {
compatible = "qcom,wcd9385-codec";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
vdd-rxtx-supply = <&vreg_l18b_1p8>;
vdd-io-supply = <&vreg_l18b_1p8>;
vdd-buck-supply = <&vreg_l17b_1p8>;
vdd-mic-bias-supply = <&vreg_bob>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
#sound-dai-cells = <1>;
status = "disabled";
}; };
pm8350c_pwm_backlight: backlight { pm8350c_pwm_backlight: backlight {
@ -309,6 +341,10 @@ &ipa {
modem-init; modem-init;
}; };
&lpass_va_macro {
vdd-micb-supply = <&vreg_bob>;
};
/* NOTE: Not all Qcards have eDP connector stuffed */ /* NOTE: Not all Qcards have eDP connector stuffed */
&mdss_edp { &mdss_edp {
aux-bus { aux-bus {
@ -378,6 +414,24 @@ &sdhc_1 {
no-sdio; no-sdio;
}; };
&swr0 {
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
#sound-dai-cells = <1>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
&swr1 {
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
#sound-dai-cells = <1>;
qcom,tx-port-mapping = <1 2 3 4>;
};
};
uart_dbg: &uart5 { uart_dbg: &uart5 {
compatible = "qcom,geni-debug-uart"; compatible = "qcom,geni-debug-uart";
status = "okay"; status = "okay";
@ -541,7 +595,7 @@ pmic_edp_bl_pwm: pmic-edp-bl-pwm-state {
}; };
&tlmm { &tlmm {
mos_bt_en: mos-bt-en { mos_bt_en: mos-bt-en-pins {
pins = "gpio85"; pins = "gpio85";
function = "gpio"; function = "gpio";
drive-strength = <2>; drive-strength = <2>;
@ -549,7 +603,7 @@ mos_bt_en: mos-bt-en {
}; };
/* For mos_bt_uart */ /* For mos_bt_uart */
qup_uart7_sleep_cts: qup-uart7-sleep-cts { qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins {
pins = "gpio28"; pins = "gpio28";
function = "gpio"; function = "gpio";
/* /*
@ -563,7 +617,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
}; };
/* For mos_bt_uart */ /* For mos_bt_uart */
qup_uart7_sleep_rts: qup-uart7-sleep-rts { qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins {
pins = "gpio29"; pins = "gpio29";
function = "gpio"; function = "gpio";
/* /*
@ -576,7 +630,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts {
}; };
/* For mos_bt_uart */ /* For mos_bt_uart */
qup_uart7_sleep_rx: qup-uart7-sleep-rx { qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins {
pins = "gpio31"; pins = "gpio31";
function = "gpio"; function = "gpio";
/* /*
@ -588,7 +642,7 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
}; };
/* For mos_bt_uart */ /* For mos_bt_uart */
qup_uart7_sleep_tx: qup-uart7-sleep-tx { qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins {
pins = "gpio30"; pins = "gpio30";
function = "gpio"; function = "gpio";
/* /*
@ -598,15 +652,35 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx {
bias-pull-up; bias-pull-up;
}; };
ts_int_conn: ts-int-conn { ts_int_conn: ts-int-conn-pins {
pins = "gpio55"; pins = "gpio55";
function = "gpio"; function = "gpio";
bias-pull-up; bias-pull-up;
}; };
ts_rst_conn: ts-rst-conn { ts_rst_conn: ts-rst-conn-pins {
pins = "gpio54"; pins = "gpio54";
function = "gpio"; function = "gpio";
drive-strength = <2>; drive-strength = <2>;
}; };
us_euro_hs_sel: us-euro-hs-sel {
pins = "gpio81";
function = "gpio";
bias-pull-down;
drive-strength = <2>;
};
wcd_reset_n: wcd-reset-n {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
};
wcd_reset_n_sleep: wcd-reset-n-sleep {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
}; };

634
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file

File diff suppressed because it is too large Load diff

31
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View file

@ -87,7 +87,6 @@ vreg_l3b: ldo3 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
@ -97,7 +96,6 @@ vreg_l4b: ldo4 {
regulator-min-microvolt = <912000>; regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>; regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l6b: ldo6 { vreg_l6b: ldo6 {
@ -105,7 +103,6 @@ vreg_l6b: ldo6 {
regulator-min-microvolt = <880000>; regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>; regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-boot-on; regulator-boot-on;
}; };
}; };
@ -119,7 +116,6 @@ vreg_l1c: ldo1 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l7c: ldo7 { vreg_l7c: ldo7 {
@ -135,7 +131,6 @@ vreg_l13c: ldo13 {
regulator-min-microvolt = <3072000>; regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>; regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
}; };
@ -158,7 +153,6 @@ vreg_l4d: ldo4 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l6d: ldo6 { vreg_l6d: ldo6 {
@ -166,7 +160,6 @@ vreg_l6d: ldo6 {
regulator-min-microvolt = <880000>; regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>; regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l7d: ldo7 { vreg_l7d: ldo7 {
@ -174,7 +167,6 @@ vreg_l7d: ldo7 {
regulator-min-microvolt = <3072000>; regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>; regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l9d: ldo9 { vreg_l9d: ldo9 {
@ -182,7 +174,6 @@ vreg_l9d: ldo9 {
regulator-min-microvolt = <912000>; regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>; regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
}; };
}; };
@ -203,16 +194,20 @@ &qup0_i2c4 {
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; pinctrl-0 = <&qup0_i2c4_default>;
status = "okay"; status = "okay";
touchscreen@10 { touchscreen@10 {
compatible = "hid-over-i2c"; compatible = "hid-over-i2c";
reg = <0x10>; reg = <0x10>;
hid-descr-addr = <0x1>; hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>; vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&ts0_default>;
}; };
}; };
@ -228,24 +223,36 @@ &qup2_i2c5 {
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; pinctrl-0 = <&qup2_i2c5_default>;
status = "okay"; status = "okay";
touchpad@15 { touchpad@15 {
compatible = "hid-over-i2c"; compatible = "hid-over-i2c";
reg = <0x15>; reg = <0x15>;
hid-descr-addr = <0x1>; hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>; vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&tpad_default>;
wakeup-source;
}; };
keyboard@68 { keyboard@68 {
compatible = "hid-over-i2c"; compatible = "hid-over-i2c";
reg = <0x68>; reg = <0x68>;
hid-descr-addr = <0x1>; hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>; vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&kybd_default>;
wakeup-source;
}; };
}; };
@ -414,7 +421,7 @@ ts0_default: ts0-default-state {
int-n { int-n {
pins = "gpio175"; pins = "gpio175";
function = "gpio"; function = "gpio";
bias-pull-up; bias-disable;
}; };
reset-n { reset-n {

48
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View file

@ -79,7 +79,6 @@ vreg_l3b: ldo3 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-boot-on; regulator-boot-on;
}; };
@ -88,7 +87,6 @@ vreg_l4b: ldo4 {
regulator-min-microvolt = <912000>; regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>; regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l6b: ldo6 { vreg_l6b: ldo6 {
@ -96,7 +94,6 @@ vreg_l6b: ldo6 {
regulator-min-microvolt = <880000>; regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>; regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-boot-on; regulator-boot-on;
regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 regulator-always-on; // FIXME: VDD_A_EDP_0_0P9
}; };
@ -111,7 +108,6 @@ vreg_l1c: ldo1 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l12c: ldo12 { vreg_l12c: ldo12 {
@ -119,7 +115,6 @@ vreg_l12c: ldo12 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l13c: ldo13 { vreg_l13c: ldo13 {
@ -127,7 +122,6 @@ vreg_l13c: ldo13 {
regulator-min-microvolt = <3072000>; regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>; regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
}; };
@ -142,7 +136,6 @@ vreg_l3d: ldo3 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l4d: ldo4 { vreg_l4d: ldo4 {
@ -150,7 +143,6 @@ vreg_l4d: ldo4 {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l7d: ldo7 { vreg_l7d: ldo7 {
@ -158,7 +150,6 @@ vreg_l7d: ldo7 {
regulator-min-microvolt = <3072000>; regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>; regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
vreg_l9d: ldo9 { vreg_l9d: ldo9 {
@ -166,7 +157,6 @@ vreg_l9d: ldo9 {
regulator-min-microvolt = <912000>; regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>; regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
}; };
}; };
}; };
@ -187,7 +177,7 @@ &qup0_i2c4 {
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; pinctrl-0 = <&qup0_i2c4_default>;
status = "okay"; status = "okay";
@ -195,9 +185,13 @@ &qup0_i2c4 {
touchscreen@10 { touchscreen@10 {
compatible = "hid-over-i2c"; compatible = "hid-over-i2c";
reg = <0x10>; reg = <0x10>;
hid-descr-addr = <0x1>; hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>; vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&ts0_default>;
}; };
}; };
@ -213,24 +207,52 @@ &qup2_i2c5 {
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; pinctrl-0 = <&qup2_i2c5_default>;
status = "okay"; status = "okay";
touchpad@15 {
compatible = "hid-over-i2c";
reg = <0x15>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&tpad_default>;
wakeup-source;
status = "disabled";
};
touchpad@2c { touchpad@2c {
compatible = "hid-over-i2c"; compatible = "hid-over-i2c";
reg = <0x2c>; reg = <0x2c>;
hid-descr-addr = <0x20>; hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>; vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&tpad_default>;
wakeup-source;
}; };
keyboard@68 { keyboard@68 {
compatible = "hid-over-i2c"; compatible = "hid-over-i2c";
reg = <0x68>; reg = <0x68>;
hid-descr-addr = <0x1>; hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>; vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&kybd_default>;
wakeup-source;
}; };
}; };
@ -373,7 +395,7 @@ ts0_default: ts0-default-state {
int-n { int-n {
pins = "gpio175"; pins = "gpio175";
function = "gpio"; function = "gpio";
bias-pull-up; bias-disable;
}; };
reset-n { reset-n {

3
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
View file

@ -60,9 +60,8 @@ pmc8280c_gpios: gpio@8800 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
pmc8280c_lpg: lpg@e800 { pmc8280c_lpg: pwm {
compatible = "qcom,pm8350c-pwm"; compatible = "qcom,pm8350c-pwm";
reg = <0xe800>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;

4
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file

@ -1312,6 +1312,8 @@ usb_0: usb@a6f8800 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb"; interconnect-names = "usb-ddr", "apps-usb";
wakeup-source;
status = "disabled"; status = "disabled";
usb_0_dwc3: usb@a600000 { usb_0_dwc3: usb@a600000 {
@ -1364,6 +1366,8 @@ usb_1: usb@a8f8800 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
interconnect-names = "usb-ddr", "apps-usb"; interconnect-names = "usb-ddr", "apps-usb";
wakeup-source;
status = "disabled"; status = "disabled";
usb_1_dwc3: usb@a800000 { usb_1_dwc3: usb@a800000 {

18
arch/arm64/boot/dts/qcom/sdm630.dtsi
View file

@ -697,9 +697,15 @@ tsens: thermal-sensor@10ae000 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex: hwlock@1f40000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>; reg = <0x01f40000 0x20000>;
#hwlock-cells = <1>;
};
tcsr_regs_1: syscon@1f60000 {
compatible = "qcom,sdm630-tcsr", "syscon";
reg = <0x01f60000 0x20000>;
}; };
tlmm: pinctrl@3100000 { tlmm: pinctrl@3100000 {
@ -2351,12 +2357,6 @@ intc: interrupt-controller@17a00000 {
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
sound: sound { sound: sound {
}; };

16
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file

@ -522,7 +522,7 @@ &mss_pil {
&pcie0 { &pcie0 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>; vddpe-3v3-supply = <&pcie0_3p3v_dual>;
@ -540,7 +540,7 @@ &pcie0_phy {
&pcie1 { &pcie1 {
status = "okay"; status = "okay";
perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>; pinctrl-0 = <&pcie1_default_state>;
@ -1081,7 +1081,7 @@ &wcd9340{
pinctrl-names = "default"; pinctrl-names = "default";
clock-names = "extclk"; clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>;
@ -1214,8 +1214,6 @@ camera@10 {
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&cam0_default>; pinctrl-0 = <&cam0_default>;
gpios = <&tlmm 13 0>,
<&tlmm 9 GPIO_ACTIVE_LOW>;
clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
clock-names = "xvclk"; clock-names = "xvclk";
@ -1228,8 +1226,6 @@ camera@10 {
* both have to be enabled through the power management * both have to be enabled through the power management
* gpios. * gpios.
*/ */
power-domains = <&clock_camcc TITAN_TOP_GDSC>;
dovdd-supply = <&vreg_lvs1a_1p8>; dovdd-supply = <&vreg_lvs1a_1p8>;
avdd-supply = <&cam0_avdd_2v8>; avdd-supply = <&cam0_avdd_2v8>;
dvdd-supply = <&cam0_dvdd_1v2>; dvdd-supply = <&cam0_dvdd_1v2>;
@ -1255,11 +1251,9 @@ camera@60 {
reg = <0x60>; reg = <0x60>;
// CAM3_RST_N // CAM3_RST_N
enable-gpios = <&tlmm 21 0>; enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&cam3_default>; pinctrl-0 = <&cam3_default>;
gpios = <&tlmm 16 0>,
<&tlmm 21 0>;
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "xclk"; clock-names = "xclk";
@ -1273,8 +1267,6 @@ camera@60 {
* *
* No 1.2V vddd-supply regulator is used. * No 1.2V vddd-supply regulator is used.
*/ */
power-domains = <&clock_camcc TITAN_TOP_GDSC>;
vdddo-supply = <&vreg_lvs1a_1p8>; vdddo-supply = <&vreg_lvs1a_1p8>;
vdda-supply = <&cam3_avdd_2v8>; vdda-supply = <&cam3_avdd_2v8>;

12
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View file

@ -536,42 +536,42 @@ adc-chan@4c {
reg = <ADC5_XO_THERM_100K_PU>; reg = <ADC5_XO_THERM_100K_PU>;
label = "xo_therm"; label = "xo_therm";
qcom,ratiometric; qcom,ratiometric;
qcom,hw-settle-time-us = <200>; qcom,hw-settle-time = <200>;
}; };
adc-chan@4d { adc-chan@4d {
reg = <ADC5_AMUX_THM1_100K_PU>; reg = <ADC5_AMUX_THM1_100K_PU>;
label = "msm_therm"; label = "msm_therm";
qcom,ratiometric; qcom,ratiometric;
qcom,hw-settle-time-us = <200>; qcom,hw-settle-time = <200>;
}; };
adc-chan@4f { adc-chan@4f {
reg = <ADC5_AMUX_THM3_100K_PU>; reg = <ADC5_AMUX_THM3_100K_PU>;
label = "pa_therm1"; label = "pa_therm1";
qcom,ratiometric; qcom,ratiometric;
qcom,hw-settle-time-us = <200>; qcom,hw-settle-time = <200>;
}; };
adc-chan@51 { adc-chan@51 {
reg = <ADC5_AMUX_THM5_100K_PU>; reg = <ADC5_AMUX_THM5_100K_PU>;
label = "quiet_therm"; label = "quiet_therm";
qcom,ratiometric; qcom,ratiometric;
qcom,hw-settle-time-us = <200>; qcom,hw-settle-time = <200>;
}; };
adc-chan@83 { adc-chan@83 {
reg = <ADC5_VPH_PWR>; reg = <ADC5_VPH_PWR>;
label = "vph_pwr"; label = "vph_pwr";
qcom,ratiometric; qcom,ratiometric;
qcom,hw-settle-time-us = <200>; qcom,hw-settle-time = <200>;
}; };
adc-chan@85 { adc-chan@85 {
reg = <ADC5_VCOIN>; reg = <ADC5_VCOIN>;
label = "vcoin"; label = "vcoin";
qcom,ratiometric; qcom,ratiometric;
qcom,hw-settle-time-us = <200>; qcom,hw-settle-time = <200>;
}; };
}; };

2
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
View file

@ -546,7 +546,7 @@ &wcd9340{
pinctrl-names = "default"; pinctrl-names = "default";
clock-names = "extclk"; clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>;

8
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
View file

@ -126,7 +126,7 @@ vreg_tp_vddio: vreg-tp-vddio {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
gpio = <&tlmm 23 0>; gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
enable-active-high; enable-active-high;
@ -522,7 +522,7 @@ &pmi8998_wled {
}; };
&pm8998_gpio { &pm8998_gpio {
volume_up_gpio: pm8998_gpio6 { volume_up_gpio: pm8998-gpio6-state {
pinconf { pinconf {
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
function = "normal"; function = "normal";
@ -617,7 +617,7 @@ sde_dsi_active: sde-dsi-active {
pins = "gpio6", "gpio10"; pins = "gpio6", "gpio10";
function = "gpio"; function = "gpio";
drive-strength = <8>; drive-strength = <8>;
bias-disable = <0>; bias-disable;
}; };
sde_dsi_suspend: sde-dsi-suspend { sde_dsi_suspend: sde-dsi-suspend {
@ -712,7 +712,7 @@ &wcd9340 {
pinctrl-names = "default"; pinctrl-names = "default";
clock-names = "extclk"; clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>;

66
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -919,12 +919,6 @@ compute-cb@8 {
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
smp2p-cdsp { smp2p-cdsp {
compatible = "qcom,smp2p"; compatible = "qcom,smp2p";
qcom,smem = <94>, <432>; qcom,smem = <94>, <432>;
@ -2138,11 +2132,48 @@ uart15: serial@a9c000 {
llcc: system-cache-controller@1100000 { llcc: system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc"; compatible = "qcom,sdm845-llcc";
reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base"; reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
}; };
pmu@114a000 {
compatible = "qcom,sdm845-llcc-bwmon";
reg = <0 0x0114a000 0 0x1000>;
interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
operating-points-v2 = <&llcc_bwmon_opp_table>;
llcc_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
/*
* The interconnect path bandwidth taken from
* cpu4_opp_table bandwidth for gladiator_noc-mem_noc
* interconnect. This also matches the
* bandwidth table of qcom,llccbw (qcom,bw-tbl,
* bus width: 4 bytes) from msm-4.9 downstream
* kernel.
*/
opp-0 {
opp-peak-kBps = <800000>;
};
opp-1 {
opp-peak-kBps = <1804000>;
};
opp-2 {
opp-peak-kBps = <3072000>;
};
opp-3 {
opp-peak-kBps = <5412000>;
};
opp-4 {
opp-peak-kBps = <7216000>;
};
};
};
pmu@1436400 { pmu@1436400 {
compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
reg = <0 0x01436400 0 0x600>; reg = <0 0x01436400 0 0x600>;
@ -2588,9 +2619,15 @@ ipa: ipa@1e40000 {
status = "disabled"; status = "disabled";
}; };
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex: hwlock@1f40000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x40000>; reg = <0 0x01f40000 0 0x20000>;
#hwlock-cells = <1>;
};
tcsr_regs_1: syscon@1f60000 {
compatible = "qcom,sdm845-tcsr", "syscon";
reg = <0 0x01f60000 0 0x20000>;
}; };
tlmm: pinctrl@3400000 { tlmm: pinctrl@3400000 {
@ -3207,7 +3244,7 @@ mss_pil: remoteproc@4080000 {
<&pdc_reset PDC_MODEM_SYNC_RESET>; <&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset"; reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
power-domains = <&rpmhpd SDM845_CX>, power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>, <&rpmhpd SDM845_MX>,
@ -4836,7 +4873,7 @@ aoss_reset: reset-controller@c2a0000 {
aoss_qmp: power-controller@c300000 { aoss_qmp: power-controller@c300000 {
compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x100000>; reg = <0 0x0c300000 0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>; mboxes = <&apss_shared 0>;
@ -4851,6 +4888,11 @@ ebi_cdev: ebi {
}; };
}; };
sram@c3f0000 {
compatible = "qcom,sdm845-rpmh-stats";
reg = <0 0x0c3f0000 0 0x400>;
};
spmi_bus: spmi@c440000 { spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb"; compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>, reg = <0 0x0c440000 0 0x1100>,

2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View file

@ -772,7 +772,7 @@ &wcd9340{
pinctrl-names = "default"; pinctrl-names = "default";
clock-names = "extclk"; clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>;

2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
View file

@ -704,7 +704,7 @@ &wcd9340{
pinctrl-names = "default"; pinctrl-names = "default";
clock-names = "extclk"; clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>;

4
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
View file

@ -87,7 +87,7 @@ &hsusb_phy1 {
}; };
&sdc2_off_state { &sdc2_off_state {
sd-cd { sd-cd-pins {
pins = "gpio98"; pins = "gpio98";
drive-strength = <2>; drive-strength = <2>;
bias-disable; bias-disable;
@ -95,7 +95,7 @@ sd-cd {
}; };
&sdc2_on_state { &sdc2_on_state {
sd-cd { sd-cd-pins {
pins = "gpio98"; pins = "gpio98";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;

10
arch/arm64/boot/dts/qcom/sm6125.dtsi
View file

@ -387,19 +387,19 @@ tlmm: pinctrl@500000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
sdc2_off_state: sdc2-off-state { sdc2_off_state: sdc2-off-state {
clk { clk-pins {
pins = "sdc2_clk"; pins = "sdc2_clk";
drive-strength = <2>; drive-strength = <2>;
bias-disable; bias-disable;
}; };
cmd { cmd-pins {
pins = "sdc2_cmd"; pins = "sdc2_cmd";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
}; };
data { data-pins {
pins = "sdc2_data"; pins = "sdc2_data";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
@ -413,13 +413,13 @@ clk {
bias-disable; bias-disable;
}; };
cmd { cmd-pins-pins {
pins = "sdc2_cmd"; pins = "sdc2_cmd";
drive-strength = <10>; drive-strength = <10>;
bias-pull-up; bias-pull-up;
}; };
data { data-pins {
pins = "sdc2_data"; pins = "sdc2_data";
drive-strength = <10>; drive-strength = <10>;
bias-pull-up; bias-pull-up;

182
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file

@ -1,11 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
* Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
*/ */
#include <dt-bindings/clock/qcom,gcc-sm6350.h> #include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sm6350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
@ -517,6 +520,26 @@ opp-384000000 {
}; };
}; };
gpi_dma0: dma-controller@800000 {
compatible = "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <10>;
dma-channel-mask = <0x1f>;
iommus = <&apps_smmu 0x56 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_0: geniqup@8c0000 { qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup"; compatible = "qcom,geni-se-qup";
reg = <0x0 0x8c0000 0x0 0x2000>; reg = <0x0 0x8c0000 0x0 0x2000>;
@ -537,8 +560,15 @@ i2c0: i2c@880000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>; pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled"; status = "disabled";
}; };
@ -550,12 +580,39 @@ i2c2: i2c@888000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>; pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled"; status = "disabled";
}; };
}; };
gpi_dma1: dma-controller@900000 {
compatible = "qcom,sm6350-gpi-dma";
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <10>;
dma-channel-mask = <0x3f>;
iommus = <&apps_smmu 0x4d6 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_1: geniqup@9c0000 { qupv3_id_1: geniqup@9c0000 {
compatible = "qcom,geni-se-qup"; compatible = "qcom,geni-se-qup";
reg = <0x0 0x9c0000 0x0 0x2000>; reg = <0x0 0x9c0000 0x0 0x2000>;
@ -576,8 +633,15 @@ i2c6: i2c@980000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>; pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled"; status = "disabled";
}; };
@ -589,8 +653,15 @@ i2c7: i2c@984000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>; pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled"; status = "disabled";
}; };
@ -602,8 +673,15 @@ i2c8: i2c@988000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>; pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled"; status = "disabled";
}; };
@ -615,6 +693,9 @@ uart9: serial@98c000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>; pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled"; status = "disabled";
}; };
@ -626,13 +707,67 @@ i2c10: i2c@990000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>; pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled"; status = "disabled";
}; };
}; };
config_noc: interconnect@1500000 {
compatible = "qcom,sm6350-config-noc";
reg = <0 0x01500000 0 0x28000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sm6350-system-noc";
reg = <0 0x01620000 0 0x17080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clk_virt: interconnect-clk-virt {
compatible = "qcom,sm6350-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm6350-aggre1-noc";
reg = <0 0x016e0000 0 0x15080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm6350-aggre2-noc";
reg = <0 0x01700000 0 0x1f880>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
compute_noc: interconnect-compute-noc {
compatible = "qcom,sm6350-compute-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sm6350-mmss-noc";
reg = <0 0x01740000 0 0x1c100>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_hc: ufs@1d84000 { ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sm6350-ufshc", "qcom,ufshc", compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0"; "jedec,ufs-2.0";
@ -933,6 +1068,10 @@ sdhc_2: mmc@8804000 {
<&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>; <&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo"; clock-names = "iface", "core", "xo";
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";
qcom,dll-config = <0x0007642c>; qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>; qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM6350_CX>; power-domains = <&rpmhpd SM6350_CX>;
@ -947,11 +1086,15 @@ sdhc2_opp_table: opp-table {
opp-100000000 { opp-100000000 {
opp-hz = /bits/ 64 <100000000>; opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs_l1>; required-opps = <&rpmhpd_opp_svs_l1>;
opp-peak-kBps = <790000 131000>;
opp-avg-kBps = <50000 50000>;
}; };
opp-202000000 { opp-202000000 {
opp-hz = /bits/ 64 <202000000>; opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_nom>; required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <3190000 294000>;
opp-avg-kBps = <261438 300000>;
}; };
}; };
}; };
@ -1017,12 +1160,33 @@ dp_phy: dp-phy@88ea200 {
}; };
}; };
dc_noc: interconnect@9160000 {
compatible = "qcom,sm6350-dc-noc";
reg = <0 0x09160000 0 0x3200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system-cache-controller@9200000 { system-cache-controller@9200000 {
compatible = "qcom,sm6350-llcc"; compatible = "qcom,sm6350-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base"; reg-names = "llcc_base", "llcc_broadcast_base";
}; };
gem_noc: interconnect@9680000 {
compatible = "qcom,sm6350-gem-noc";
reg = <0 0x09680000 0 0x3e200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
npu_noc: interconnect@9990000 {
compatible = "qcom,sm6350-npu-noc";
reg = <0 0x09990000 0 0x1600>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
usb_1: usb@a6f8800 { usb_1: usb@a6f8800 {
compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>; reg = <0 0x0a6f8800 0 0x400>;
@ -1054,6 +1218,10 @@ usb_1: usb@a6f8800 {
resets = <&gcc GCC_USB30_PRIM_BCR>; resets = <&gcc GCC_USB30_PRIM_BCR>;
interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";
usb_1_dwc3: usb@a600000 { usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3"; compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>; reg = <0 0x0a600000 0 0xcd00>;
@ -1146,49 +1314,49 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>; gpio-ranges = <&tlmm 0 0 157>;
qup_uart9_default: qup-uart9-default { qup_uart9_default: qup-uart9-default-state {
pins = "gpio25", "gpio26"; pins = "gpio25", "gpio26";
function = "qup13_f2"; function = "qup13_f2";
drive-strength = <2>; drive-strength = <2>;
bias-disable; bias-disable;
}; };
qup_i2c0_default: qup-i2c0-default { qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio0", "gpio1"; pins = "gpio0", "gpio1";
function = "qup00"; function = "qup00";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
}; };
qup_i2c2_default: qup-i2c2-default { qup_i2c2_default: qup-i2c2-default-state {
pins = "gpio45", "gpio46"; pins = "gpio45", "gpio46";
function = "qup02"; function = "qup02";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
}; };
qup_i2c6_default: qup-i2c6-default { qup_i2c6_default: qup-i2c6-default-state {
pins = "gpio13", "gpio14"; pins = "gpio13", "gpio14";
function = "qup10"; function = "qup10";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
}; };
qup_i2c7_default: qup-i2c7-default { qup_i2c7_default: qup-i2c7-default-state {
pins = "gpio27", "gpio28"; pins = "gpio27", "gpio28";
function = "qup11"; function = "qup11";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
}; };
qup_i2c8_default: qup-i2c8-default { qup_i2c8_default: qup-i2c8-default-state {
pins = "gpio19", "gpio20"; pins = "gpio19", "gpio20";
function = "qup12"; function = "qup12";
drive-strength = <2>; drive-strength = <2>;
bias-pull-up; bias-pull-up;
}; };
qup_i2c10_default: qup-i2c10-default { qup_i2c10_default: qup-i2c10-default-state {
pins = "gpio4", "gpio5"; pins = "gpio4", "gpio5";
function = "qup14"; function = "qup14";
drive-strength = <2>; drive-strength = <2>;

67
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View file

@ -12,6 +12,7 @@
#include "sm7225.dtsi" #include "sm7225.dtsi"
#include "pm6150l.dtsi" #include "pm6150l.dtsi"
#include "pm6350.dtsi" #include "pm6350.dtsi"
#include "pm7250b.dtsi"
/ { / {
model = "Fairphone 4"; model = "Fairphone 4";
@ -70,6 +71,36 @@ memory@efe01000 {
qcom,vmid = <15>; qcom,vmid = <15>;
}; };
}; };
thermal-zones {
chg-skin-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
conn-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
}; };
&adsp { &adsp {
@ -353,6 +384,42 @@ &pm6350_resin {
linux,code = <KEY_VOLUMEDOWN>; linux,code = <KEY_VOLUMEDOWN>;
}; };
&pm7250b_adc {
adc-chan@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "charger_skin_therm";
};
adc-chan@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "conn_therm";
};
};
&pm7250b_adc_tm {
status = "okay";
charger-skin-therm@0 {
reg = <0>;
io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
conn-therm@1 {
reg = <1>;
io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&qupv3_id_1 { &qupv3_id_1 {
status = "okay"; status = "okay";
}; };

18
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -585,12 +585,6 @@ scm: scm {
}; };
}; };
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
/* We expect the bootloader to fill in the size */ /* We expect the bootloader to fill in the size */
@ -2054,9 +2048,15 @@ ipa_virt: interconnect@1e00000 {
qcom,bcm-voters = <&apps_bcm_voter>; qcom,bcm-voters = <&apps_bcm_voter>;
}; };
tcsr_mutex_regs: syscon@1f40000 { tcsr_mutex: hwlock@1f40000 {
compatible = "syscon"; compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>; reg = <0x0 0x01f40000 0x0 0x20000>;
#hwlock-cells = <1>;
};
tcsr_regs_1: syscon@1f60000 {
compatible = "qcom,sm8150-tcsr", "syscon";
reg = <0x0 0x01f60000 0x0 0x20000>;
}; };
remoteproc_slpi: remoteproc@2400000 { remoteproc_slpi: remoteproc@2400000 {

2
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
View file

@ -635,7 +635,7 @@ &soc {
wcd938x: codec { wcd938x: codec {
compatible = "qcom,wcd9380-codec"; compatible = "qcom,wcd9380-codec";
#sound-dai-cells = <1>; #sound-dai-cells = <1>;
reset-gpios = <&tlmm 32 0>; reset-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-rxtx-supply = <&vreg_s4a_1p8>; vdd-rxtx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>; vdd-io-supply = <&vreg_s4a_1p8>;

56
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file

@ -1792,7 +1792,7 @@ mmss_noc: interconnect@1740000 {
}; };
pcie0: pci@1c00000 { pcie0: pci@1c00000 {
compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>, reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>, <0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>, <0 0x60000f20 0 0xa8>,
@ -1810,8 +1810,16 @@ pcie0: pci@1c00000 {
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
interrupt-names = "msi"; <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>; interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1893,7 +1901,7 @@ pcie0_lane: phy@1c06200 {
}; };
pcie1: pci@1c08000 { pcie1: pci@1c08000 {
compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>, reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>, <0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>, <0 0x40000f20 0 0xa8>,
@ -2001,7 +2009,7 @@ pcie1_lane: phy@1c0e200 {
}; };
pcie2: pci@1c10000 { pcie2: pci@1c10000 {
compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>, reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>, <0 0x64000000 0 0xf1d>,
<0 0x64000f20 0 0xa8>, <0 0x64000f20 0 0xa8>,
@ -3571,6 +3579,25 @@ dsi0_out: endpoint {
}; };
}; };
}; };
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
}; };
dsi0_phy: dsi-phy@ae94400 { dsi0_phy: dsi-phy@ae94400 {
@ -3663,25 +3690,6 @@ dsi1_phy: dsi-phy@ae96400 {
clock-names = "iface", "ref"; clock-names = "iface", "ref";
status = "disabled"; status = "disabled";
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
}; };
}; };

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