ixgbe: Add X550 support function pointers
This patch extends the function pointer structure to include the new X550 class MAC types. This creates a new file ixgbe_x550.c that contains all of the new methods. Because of similarities to the X540 part in some cases we just use it's methods where they can be used without any modification. These exported functions are now defined in the new ixgbe_x540.h file. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Don Skidmore
Jeff Kirsher
parent
735c35afed
commit
6a14ee0cfb
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@ -34,7 +34,7 @@ obj-$(CONFIG_IXGBE) += ixgbe.o
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ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \
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ixgbe_82599.o ixgbe_82598.o ixgbe_phy.o ixgbe_sriov.o \
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ixgbe_mbx.o ixgbe_x540.o ixgbe_lib.o ixgbe_ptp.o
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ixgbe_mbx.o ixgbe_x540.o ixgbe_x550.o ixgbe_lib.o ixgbe_ptp.o
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ixgbe-$(CONFIG_IXGBE_DCB) += ixgbe_dcb.o ixgbe_dcb_82598.o \
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ixgbe_dcb_82599.o ixgbe_dcb_nl.o
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@ -815,11 +815,15 @@ enum ixgbe_boards {
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board_82598,
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board_82599,
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board_X540,
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board_X550,
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board_X550EM_x,
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};
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extern struct ixgbe_info ixgbe_82598_info;
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extern struct ixgbe_info ixgbe_82599_info;
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extern struct ixgbe_info ixgbe_X540_info;
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extern struct ixgbe_info ixgbe_X550_info;
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extern struct ixgbe_info ixgbe_X550EM_x_info;
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#ifdef CONFIG_IXGBE_DCB
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extern const struct dcbnl_rtnl_ops dcbnl_ops;
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#endif
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@ -3479,9 +3479,9 @@ static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
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* Communicates with the manageability block. On success return 0
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* else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
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**/
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static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
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u32 length, u32 timeout,
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bool return_data)
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s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
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u32 length, u32 timeout,
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bool return_data)
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{
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u32 hicr, i, bi, fwsts;
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u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
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@ -110,6 +110,8 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
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s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
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s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
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u8 build, u8 ver);
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s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
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u32 length, u32 timeout, bool return_data);
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void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
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bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
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@ -81,9 +81,11 @@ static const char ixgbe_copyright[] =
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"Copyright (c) 1999-2014 Intel Corporation.";
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static const struct ixgbe_info *ixgbe_info_tbl[] = {
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[board_82598] = &ixgbe_82598_info,
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[board_82599] = &ixgbe_82599_info,
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[board_X540] = &ixgbe_X540_info,
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[board_82598] = &ixgbe_82598_info,
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[board_82599] = &ixgbe_82599_info,
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[board_X540] = &ixgbe_X540_info,
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[board_X550] = &ixgbe_X550_info,
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[board_X550EM_x] = &ixgbe_X550EM_x_info,
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};
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/* ixgbe_pci_tbl - PCI Device ID Table
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@ -125,6 +127,9 @@ static const struct pci_device_id ixgbe_pci_tbl[] = {
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{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
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{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
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{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
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{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
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{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
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{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
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/* required last entry */
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{0, }
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};
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@ -77,6 +77,11 @@
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#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
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#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
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#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
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#define IXGBE_CS4227 0xBE /* CS4227 address */
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#define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */
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#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
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#define IXGBE_CS4227_EDC_MODE_SR 0x0004
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/* Flow control defines */
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#define IXGBE_TAF_SYM_PAUSE 0x400
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#define IXGBE_TAF_ASM_PAUSE 0x800
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@ -110,7 +115,6 @@
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/* SFP+ SFF-8472 Compliance code */
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#define IXGBE_SFF_SFF_8472_UNSUP 0x00
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s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
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s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
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s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
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s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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@ -74,6 +74,17 @@
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#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
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#define IXGBE_DEV_ID_X540T1 0x1560
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#define IXGBE_DEV_ID_X550T 0x1563
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#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
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#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
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#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
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#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
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#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
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#define IXGBE_DEV_ID_X550_VF_HV 0x1564
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#define IXGBE_DEV_ID_X550_VF 0x1565
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#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
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#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
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/* VF Device IDs */
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#define IXGBE_DEV_ID_82599_VF 0x10ED
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#define IXGBE_DEV_ID_X540_VF 0x1515
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@ -741,6 +752,24 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_LDPCECL 0x0E820
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#define IXGBE_LDPCECH 0x0E821
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/* MII clause 22/28 definitions */
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#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
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#define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register */
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#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */
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#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
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/* Management */
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#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
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#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
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@ -1142,6 +1171,13 @@ struct ixgbe_thermal_sensor_data {
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/* MDIO definitions */
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#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
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#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
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#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
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#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
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#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
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#define IXGBE_TWINAX_DEV 1
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#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
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#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
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@ -1151,9 +1187,23 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
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#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
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#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
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#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */
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#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */
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#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
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#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
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#define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
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#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Stat Reg */
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#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Tx Dis Reg */
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#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Tx Dis */
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/* MII clause 22/28 definitions */
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#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
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@ -1697,12 +1747,14 @@ enum {
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#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
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/* SW_FW_SYNC/GSSR definitions */
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#define IXGBE_GSSR_EEP_SM 0x0001
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#define IXGBE_GSSR_PHY0_SM 0x0002
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#define IXGBE_GSSR_PHY1_SM 0x0004
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#define IXGBE_GSSR_MAC_CSR_SM 0x0008
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#define IXGBE_GSSR_FLASH_SM 0x0010
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#define IXGBE_GSSR_SW_MNG_SM 0x0400
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#define IXGBE_GSSR_EEP_SM 0x0001
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#define IXGBE_GSSR_PHY0_SM 0x0002
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#define IXGBE_GSSR_PHY1_SM 0x0004
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#define IXGBE_GSSR_MAC_CSR_SM 0x0008
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#define IXGBE_GSSR_FLASH_SM 0x0010
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#define IXGBE_GSSR_SW_MNG_SM 0x0400
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#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */
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#define IXGBE_GSSR_I2C_MASK 0x1800
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/* FW Status register bitmask */
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#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
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@ -1736,27 +1788,32 @@ enum {
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#define IXGBE_PBANUM_LENGTH 11
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/* Checksum and EEPROM pointers */
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#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
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#define IXGBE_EEPROM_CHECKSUM 0x3F
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#define IXGBE_EEPROM_SUM 0xBABA
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#define IXGBE_PCIE_ANALOG_PTR 0x03
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#define IXGBE_ATLAS0_CONFIG_PTR 0x04
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#define IXGBE_PHY_PTR 0x04
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#define IXGBE_ATLAS1_CONFIG_PTR 0x05
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#define IXGBE_OPTION_ROM_PTR 0x05
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#define IXGBE_PCIE_GENERAL_PTR 0x06
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#define IXGBE_PCIE_CONFIG0_PTR 0x07
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#define IXGBE_PCIE_CONFIG1_PTR 0x08
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#define IXGBE_CORE0_PTR 0x09
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#define IXGBE_CORE1_PTR 0x0A
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#define IXGBE_MAC0_PTR 0x0B
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#define IXGBE_MAC1_PTR 0x0C
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#define IXGBE_CSR0_CONFIG_PTR 0x0D
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#define IXGBE_CSR1_CONFIG_PTR 0x0E
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#define IXGBE_FW_PTR 0x0F
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#define IXGBE_PBANUM0_PTR 0x15
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#define IXGBE_PBANUM1_PTR 0x16
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#define IXGBE_FREE_SPACE_PTR 0X3E
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#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
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#define IXGBE_EEPROM_CHECKSUM 0x3F
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#define IXGBE_EEPROM_SUM 0xBABA
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#define IXGBE_PCIE_ANALOG_PTR 0x03
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#define IXGBE_ATLAS0_CONFIG_PTR 0x04
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#define IXGBE_PHY_PTR 0x04
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#define IXGBE_ATLAS1_CONFIG_PTR 0x05
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#define IXGBE_OPTION_ROM_PTR 0x05
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#define IXGBE_PCIE_GENERAL_PTR 0x06
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#define IXGBE_PCIE_CONFIG0_PTR 0x07
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#define IXGBE_PCIE_CONFIG1_PTR 0x08
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#define IXGBE_CORE0_PTR 0x09
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#define IXGBE_CORE1_PTR 0x0A
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#define IXGBE_MAC0_PTR 0x0B
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#define IXGBE_MAC1_PTR 0x0C
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#define IXGBE_CSR0_CONFIG_PTR 0x0D
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#define IXGBE_CSR1_CONFIG_PTR 0x0E
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#define IXGBE_PCIE_ANALOG_PTR_X550 0x02
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#define IXGBE_SHADOW_RAM_SIZE_X550 0x4000
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#define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24
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#define IXGBE_PCIE_CONFIG_SIZE 0x08
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#define IXGBE_EEPROM_LAST_WORD 0x41
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#define IXGBE_FW_PTR 0x0F
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#define IXGBE_PBANUM0_PTR 0x15
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#define IXGBE_PBANUM1_PTR 0x16
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#define IXGBE_FREE_SPACE_PTR 0X3E
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/* External Thermal Sensor Config */
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#define IXGBE_ETS_CFG 0x26
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@ -2322,13 +2379,24 @@ enum ixgbe_fdir_pballoc_type {
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#define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */
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/* CEM Support */
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#define FW_CEM_HDR_LEN 0x4
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#define FW_CEM_CMD_DRIVER_INFO 0xDD
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#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
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#define FW_CEM_CMD_RESERVED 0x0
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#define FW_CEM_UNUSED_VER 0x0
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#define FW_CEM_MAX_RETRIES 3
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#define FW_CEM_RESP_STATUS_SUCCESS 0x1
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#define FW_CEM_HDR_LEN 0x4
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#define FW_CEM_CMD_DRIVER_INFO 0xDD
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#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
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#define FW_CEM_CMD_RESERVED 0x0
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#define FW_CEM_UNUSED_VER 0x0
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#define FW_CEM_MAX_RETRIES 3
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#define FW_CEM_RESP_STATUS_SUCCESS 0x1
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#define FW_READ_SHADOW_RAM_CMD 0x31
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#define FW_READ_SHADOW_RAM_LEN 0x6
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#define FW_WRITE_SHADOW_RAM_CMD 0x33
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#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
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#define FW_SHADOW_RAM_DUMP_CMD 0x36
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#define FW_SHADOW_RAM_DUMP_LEN 0
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#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
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#define FW_NVM_DATA_OFFSET 3
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#define FW_MAX_READ_BUFFER_SIZE 1024
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#define FW_DISABLE_RXEN_CMD 0xDE
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#define FW_DISABLE_RXEN_LEN 0x1
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/* Host Interface Command Structures */
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struct ixgbe_hic_hdr {
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@ -2341,6 +2409,25 @@ struct ixgbe_hic_hdr {
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u8 checksum;
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};
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struct ixgbe_hic_hdr2_req {
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u8 cmd;
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u8 buf_lenh;
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u8 buf_lenl;
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u8 checksum;
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};
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struct ixgbe_hic_hdr2_rsp {
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u8 cmd;
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u8 buf_lenl;
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u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
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u8 checksum;
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};
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union ixgbe_hic_hdr2 {
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struct ixgbe_hic_hdr2_req req;
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struct ixgbe_hic_hdr2_rsp rsp;
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};
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struct ixgbe_hic_drv_info {
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struct ixgbe_hic_hdr hdr;
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u8 port_num;
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|
|
@ -2352,6 +2439,32 @@ struct ixgbe_hic_drv_info {
|
|||
u16 pad2; /* end spacing to ensure length is mult. of dword2 */
|
||||
};
|
||||
|
||||
/* These need to be dword aligned */
|
||||
struct ixgbe_hic_read_shadow_ram {
|
||||
union ixgbe_hic_hdr2 hdr;
|
||||
u32 address;
|
||||
u16 length;
|
||||
u16 pad2;
|
||||
u16 data;
|
||||
u16 pad3;
|
||||
};
|
||||
|
||||
struct ixgbe_hic_write_shadow_ram {
|
||||
union ixgbe_hic_hdr2 hdr;
|
||||
u32 address;
|
||||
u16 length;
|
||||
u16 pad2;
|
||||
u16 data;
|
||||
u16 pad3;
|
||||
};
|
||||
|
||||
struct ixgbe_hic_disable_rxen {
|
||||
struct ixgbe_hic_hdr hdr;
|
||||
u8 port_number;
|
||||
u8 pad2;
|
||||
u16 pad3;
|
||||
};
|
||||
|
||||
/* Transmit Descriptor - Advanced */
|
||||
union ixgbe_adv_tx_desc {
|
||||
struct {
|
||||
|
|
@ -2628,6 +2741,9 @@ enum ixgbe_phy_type {
|
|||
ixgbe_phy_none,
|
||||
ixgbe_phy_tn,
|
||||
ixgbe_phy_aq,
|
||||
ixgbe_phy_x550em_kr,
|
||||
ixgbe_phy_x550em_kx4,
|
||||
ixgbe_phy_x550em_ext_t,
|
||||
ixgbe_phy_cu_unknown,
|
||||
ixgbe_phy_qt,
|
||||
ixgbe_phy_xaui,
|
||||
|
|
@ -2940,6 +3056,11 @@ struct ixgbe_mac_operations {
|
|||
s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
|
||||
s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
|
||||
s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
|
||||
|
||||
/* DMA Coalescing */
|
||||
s32 (*dmac_config)(struct ixgbe_hw *hw);
|
||||
s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
|
||||
s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
|
||||
};
|
||||
|
||||
struct ixgbe_phy_operations {
|
||||
|
|
@ -2952,6 +3073,7 @@ struct ixgbe_phy_operations {
|
|||
s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
|
||||
s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
|
||||
s32 (*setup_link)(struct ixgbe_hw *);
|
||||
s32 (*setup_internal_link)(struct ixgbe_hw *);
|
||||
s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
|
||||
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
|
||||
s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
|
||||
|
|
@ -3122,4 +3244,71 @@ struct ixgbe_info {
|
|||
#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
|
||||
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
|
||||
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P == 0) ? (0x4010) : (0x8010))
|
||||
#define IXGBE_KRM_LINK_CTRL_1(P) ((P == 0) ? (0x420C) : (0x820C))
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P == 0) ? (0x4634) : (0x8634))
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P == 0) ? (0x4638) : (0x8638))
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P == 0) ? (0x4B00) : (0x8B00))
|
||||
#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P == 0) ? (0x4E00) : (0x8E00))
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P == 0) ? (0x5520) : (0x9520))
|
||||
#define IXGBE_KRM_RX_ANA_CTL(P) ((P == 0) ? (0x5A00) : (0x9A00))
|
||||
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
|
||||
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
|
||||
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
|
||||
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
|
||||
|
||||
#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
|
||||
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
|
||||
|
||||
#define IXGBE_KX4_LINK_CNTL_1 0x4C
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX (1 << 16)
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 (1 << 17)
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX (1 << 24)
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 (1 << 25)
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE (1 << 29)
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP (1 << 30)
|
||||
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART (1 << 31)
|
||||
|
||||
#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
|
||||
#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
|
||||
|
||||
#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
|
||||
#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
|
||||
#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
|
||||
#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
|
||||
(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
|
||||
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20
|
||||
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
|
||||
(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
|
||||
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
|
||||
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
|
||||
#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
|
||||
#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
|
||||
#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
|
||||
#define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1
|
||||
#define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2
|
||||
#define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3
|
||||
|
||||
#endif /* _IXGBE_TYPE_H_ */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
#include "ixgbe.h"
|
||||
#include "ixgbe_phy.h"
|
||||
#include "ixgbe_x540.h"
|
||||
|
||||
#define IXGBE_X540_MAX_TX_QUEUES 128
|
||||
#define IXGBE_X540_MAX_RX_QUEUES 128
|
||||
|
|
@ -42,17 +43,15 @@
|
|||
|
||||
static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
|
||||
static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
|
||||
static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);
|
||||
static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);
|
||||
static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
|
||||
static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
|
||||
|
||||
static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
|
||||
enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
|
||||
{
|
||||
return ixgbe_media_type_copper;
|
||||
}
|
||||
|
||||
static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
|
||||
s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
|
||||
{
|
||||
struct ixgbe_mac_info *mac = &hw->mac;
|
||||
|
||||
|
|
@ -76,9 +75,8 @@ static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
|
|||
* @speed: new link speed
|
||||
* @autoneg_wait_to_complete: true when waiting for completion is needed
|
||||
**/
|
||||
static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
|
||||
ixgbe_link_speed speed,
|
||||
bool autoneg_wait_to_complete)
|
||||
s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg_wait_to_complete)
|
||||
{
|
||||
return hw->phy.ops.setup_link_speed(hw, speed,
|
||||
autoneg_wait_to_complete);
|
||||
|
|
@ -92,7 +90,7 @@ static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
|
|||
* and clears all interrupts, perform a PHY reset, and perform a link (MAC)
|
||||
* reset.
|
||||
**/
|
||||
static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
|
||||
s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 status;
|
||||
u32 ctrl, i;
|
||||
|
|
@ -179,7 +177,7 @@ mac_reset_top:
|
|||
* and the generation start_hw function.
|
||||
* Then performs revision-specific operations, if any.
|
||||
**/
|
||||
static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
|
||||
s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 ret_val;
|
||||
|
||||
|
|
@ -197,7 +195,7 @@ static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
|
|||
* Initializes the EEPROM parameters ixgbe_eeprom_info within the
|
||||
* ixgbe_hw struct in order to set up EEPROM access.
|
||||
**/
|
||||
static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
|
||||
s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
|
||||
{
|
||||
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
|
||||
u32 eec;
|
||||
|
|
@ -565,7 +563,7 @@ static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
|
|||
* Acquires the SWFW semaphore thought the SW_FW_SYNC register for
|
||||
* the specified function (CSR, PHY0, PHY1, NVM, Flash)
|
||||
**/
|
||||
static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
|
||||
s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
|
||||
{
|
||||
u32 swfw_sync;
|
||||
u32 swmask = mask;
|
||||
|
|
@ -633,7 +631,7 @@ static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
|
|||
* Releases the SWFW semaphore through the SW_FW_SYNC register
|
||||
* for the specified function (CSR, PHY0, PHY1, EVM, Flash)
|
||||
**/
|
||||
static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
|
||||
void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
|
||||
{
|
||||
u32 swfw_sync;
|
||||
u32 swmask = mask;
|
||||
|
|
@ -720,7 +718,7 @@ static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
|
|||
* Devices that implement the version 2 interface:
|
||||
* X540
|
||||
**/
|
||||
static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
|
||||
s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
|
||||
{
|
||||
u32 macc_reg;
|
||||
u32 ledctl_reg;
|
||||
|
|
@ -756,7 +754,7 @@ static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
|
|||
* Devices that implement the version 2 interface:
|
||||
* X540
|
||||
**/
|
||||
static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
|
||||
s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
|
||||
{
|
||||
u32 macc_reg;
|
||||
u32 ledctl_reg;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* Intel 10 Gigabit PCI Express Linux driver
|
||||
* Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
* Contact Information:
|
||||
* Linux NICS <linux.nics@intel.com>
|
||||
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "ixgbe_type.h"
|
||||
|
||||
s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg_wait_to_complete);
|
||||
s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
|
||||
enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg_wait_to_complete);
|
||||
s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);
|
||||
s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);
|
||||
s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);
|
||||
void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);
|
||||
s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue