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ARM: ixp4xx: Delete Coyote and IXDPG425 boardfiles 

These boards are replaced with the corresponding device trees.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2021-07-28 17:14:10 +02:00
parent 73d04ca5f4
commit 6dc9b80c2a
5 changed files with 0 additions and 282 deletions
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16
arch/arm/mach-ixp4xx/Kconfig
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@ -17,14 +17,6 @@ config MACH_IXP4XX_OF
help
Say 'Y' here to support Device Tree-based IXP4xx platforms.
config ARCH_ADI_COYOTE
bool "Coyote"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the ADI
Engineering Coyote Gateway Reference Platform. For more
information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_GATEWAY7001
bool "Gateway 7001"
depends on IXP4XX_PCI_LEGACY
@ -33,14 +25,6 @@ config MACH_GATEWAY7001
7001 Access Point. For more information on this platform,
see http://openwrt.org
config MACH_IXDPG425
bool "IXDPG425"
depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Intel's
IXDPG425 Development Platform (Also known as Montajade).
For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.
config MACH_GORAMO_MLR
bool "GORAMO Multi Link Router"
help

4
arch/arm/mach-ixp4xx/Makefile
View File

@ -9,16 +9,12 @@ obj-pci-n :=
# Device tree platform
obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o
obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
obj-y += common.o
obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
obj-$(CONFIG_MACH_FSG) += fsg-setup.o

62
arch/arm/mach-ixp4xx/coyote-pci.c
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@ -1,62 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/coyote-pci.c
*
* PCI setup routines for ADI Engineering Coyote platform
*
* Copyright (C) 2002 Jungo Software Technologies.
* Copyright (C) 2003 MontaVista Softwrae, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@mvista.com>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include "irqs.h"
#define SLOT0_DEVID 14
#define SLOT1_DEVID 15
/* PCI controller GPIO to IRQ pin mappings */
#define SLOT0_INTA 6
#define SLOT1_INTA 11
void __init coyote_pci_preinit(void)
{
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == SLOT0_DEVID)
return IXP4XX_GPIO_IRQ(SLOT0_INTA);
else if (slot == SLOT1_DEVID)
return IXP4XX_GPIO_IRQ(SLOT1_INTA);
else return -1;
}
struct hw_pci coyote_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = coyote_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = coyote_map_irq,
};
int __init coyote_pci_init(void)
{
if (machine_is_adi_coyote())
pci_common_init(&coyote_pci);
return 0;
}
subsys_initcall(coyote_pci_init);

144
arch/arm/mach-ixp4xx/coyote-setup.c
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@ -1,144 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/mach-ixp4xx/coyote-setup.c
*
* Board setup for ADI Engineering and IXDGP425 boards
*
* Copyright (C) 2003-2005 MontaVista Software, Inc.
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "irqs.h"
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
#define COYOTE_IDE_REGION_SIZE 0x1000
#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
static struct flash_platform_data coyote_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource coyote_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device coyote_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = {
.platform_data = &coyote_flash_data,
},
.num_resources = 1,
.resource = &coyote_flash_resource,
};
static struct resource coyote_uart_resource = {
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
};
static struct plat_serial8250_port coyote_uart_data[] = {
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device coyote_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = coyote_uart_data,
},
.num_resources = 1,
.resource = &coyote_uart_resource,
};
static struct platform_device *coyote_devices[] __initdata = {
&coyote_flash,
&coyote_uart
};
static void __init coyote_init(void)
{
ixp4xx_sys_init();
coyote_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
coyote_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
if (machine_is_ixdpg425()) {
coyote_uart_data[0].membase =
(char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
coyote_uart_data[0].mapbase = IXP4XX_UART1_BASE_PHYS;
coyote_uart_data[0].irq = IRQ_IXP4XX_UART1;
}
platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
}
#ifdef CONFIG_ARCH_ADI_COYOTE
MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = coyote_init,
#if defined(CONFIG_PCI)
.dma_zone_size = SZ_64M,
#endif
.restart = ixp4xx_restart,
MACHINE_END
#endif
/*
* IXDPG425 is identical to Coyote except for which serial port
* is connected.
*/
#ifdef CONFIG_MACH_IXDPG425
MACHINE_START(IXDPG425, "Intel IXDPG425")
/* Maintainer: MontaVista Software, Inc. */
.map_io = ixp4xx_map_io,
.init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
.init_time = ixp4xx_timer_init,
.atag_offset = 0x100,
.init_machine = coyote_init,
.restart = ixp4xx_restart,
MACHINE_END
#endif

56
arch/arm/mach-ixp4xx/ixdpg425-pci.c
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@ -1,56 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-ixp4xx/ixdpg425-pci.c
*
* PCI setup routines for Intel IXDPG425 Platform
*
* Copyright (C) 2004 MontaVista Softwrae, Inc.
*
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/mach/pci.h>
#include "irqs.h"
void __init ixdpg425_pci_preinit(void)
{
irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 12 || slot == 13)
return IRQ_IXP4XX_GPIO7;
else if (slot == 14)
return IRQ_IXP4XX_GPIO6;
else return -1;
}
struct hw_pci ixdpg425_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = ixdpg425_pci_preinit,
.setup = ixp4xx_setup,
.map_irq = ixdpg425_map_irq,
};
int __init ixdpg425_pci_init(void)
{
if (machine_is_ixdpg425())
pci_common_init(&ixdpg425_pci);
return 0;
}
subsys_initcall(ixdpg425_pci_init);