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i.MX arm64 device tree for 6.5: 

- New board support: i.MX8MM based Emtop SoM & Baseboard, NXP i.MX8MM EVKB
   board, i.MX8MP based Gateworks Venice gw7905-2x device.
 - A series from Adam Ford to add Camera and Audio support for i.MX8M
   based Beacon boards.
 - Add Audio output support for i.MX8MP TQMa8MPxL/MBa8MPxL board.
 - Add HDMI and display support for imx8mm-evk and imx8mm-phg board.
 - Add coresight trace devices support for i.MX8MP SoC.
 - A couple of changes from Krzysztof Kozlowski to add missing cache
   properties.
 - A couple of changes from Laurent Pinchart to add CSIS and ISI devices
   for i.MX8MP SoC.
 - A series from Marek Vasut to add more devices for i.MX8MP, and enable
   SAI audio on i.MX8MP DHCOM PDK2 and PDK3.
 - Correct GSC vdd_bat data size for Gateworks Venice devices.
 - Add more device support for i.MX93, Watchdog, OCOTP, idle states, DDR
   performance monitor, etc.
 - Small and random clean-ups and device node additions.
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Merge tag 'imx-dt64-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree for 6.5:

- New board support: i.MX8MM based Emtop SoM & Baseboard, NXP i.MX8MM EVKB
  board, i.MX8MP based Gateworks Venice gw7905-2x device.
- A series from Adam Ford to add Camera and Audio support for i.MX8M
  based Beacon boards.
- Add Audio output support for i.MX8MP TQMa8MPxL/MBa8MPxL board.
- Add HDMI and display support for imx8mm-evk and imx8mm-phg board.
- Add coresight trace devices support for i.MX8MP SoC.
- A couple of changes from Krzysztof Kozlowski to add missing cache
  properties.
- A couple of changes from Laurent Pinchart to add CSIS and ISI devices
  for i.MX8MP SoC.
- A series from Marek Vasut to add more devices for i.MX8MP, and enable
  SAI audio on i.MX8MP DHCOM PDK2 and PDK3.
- Correct GSC vdd_bat data size for Gateworks Venice devices.
- Add more device support for i.MX93, Watchdog, OCOTP, idle states, DDR
  performance monitor, etc.
- Small and random clean-ups and device node additions.

* tag 'imx-dt64-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (47 commits)
  arm64: dts: imx8mq: Pass address-cells/size-cells to mipi_dsi
  arm64: dts: imx8mq: Use 'dsi' as node name
  arm64: dts: imx8mp-venice-gw702x: fix GSC vdd_bat data size
  arm64: dts: imx8mq-tqma8mq-mba8mx: Remove invalid properties
  arm64: dts: imx8mq: Add missing pci property
  arm64: dts: imx8mq: Fix lcdif clocks
  arm64: dts: imx8mq: Fix lcdif compatible
  arm64: dts: imx8mp: don't initialize audio clocks from CCM node
  arm64: dts: imx8mm-venice: Fix GSC vdd_bat data size.
  arm64: dts: imx8mp: Add coresight trace components
  arm64: dts: imx93: add ddr performance monitor node
  arm64: dts: imx8mm-phg: Add display support
  arm64: dts: tqma8mqml: Add vcc supply to i2c eeproms
  arm64: dts: imx8mm-evk: Add HDMI support
  arm64: dts: imx8mn-var-som-symphony: adapt FEC pinctrl for SOMs with onboard PHY
  arm64: dts: imx8mn-var-som: add 20ms delay to ethernet regulator enable
  arm64: dts: imx8mp-msc-sm2s: Add sound card
  arm64: dts: imx8mn-beacon: Migrate sound card to simple-audio-card
  arm64: dts: imx8mp-beacon-kit: Enable WM8962 Audio CODEC
  arm64: dts: imx93: add fsl,stop-mode property to support WOL
  ...

Link: https://lore.kernel.org/r/20230610072530.418847-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-20 22:40:43 +02:00
parent f50a4e594d 8e2facfe90
commit 70cdf5e28c
41 changed files with 2727 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/freescale/Makefile
View File

@ -54,7 +54,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb
@ -99,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb

1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -47,6 +47,7 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -85,6 +85,7 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -80,6 +80,7 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -96,21 +96,25 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CPU_PW20: cpu-pw20 {

4
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -96,21 +96,25 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CPU_PW20: cpu-pw20 {

1
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@ -60,6 +60,7 @@
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

15
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Emtop Embedded Solutions
*/
/dts-v1/;
#include "imx8mm-emtop-som.dtsi"
/ {
model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1";
compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som",
"fsl,imx8mm";
};

261
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi Normal file
View File

@ -0,0 +1,261 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Emtop Embedded Solutions
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mm.dtsi"
/ {
model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";
compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
function = LED_FUNCTION_POWER;
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck3: BUCK3 {
regulator-name = "BUCK3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <945000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <1890000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <945000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3600000>;
};
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_gpio_led: emtop-gpio-led-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};
pinctrl_i2c1: emtop-i2c1-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: emtop-pmic-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart2: emtop-uart2-grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: emtop-usdhc3-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: emtop-wdog-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

67
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -19,6 +19,18 @@
reg = <0x0 0x40000000 0 0x80000000>;
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7533_out>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -303,6 +315,41 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
reg-names = "main", "cec", "edid", "packet";
adi,dsi-lanes = <4>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7533_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
adv7533_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
@ -348,6 +395,26 @@
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
ports {
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&adv7533_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;

128
arch/arm64/boot/dts/freescale/imx8mm-evkb.dts Normal file
View File

@ -0,0 +1,128 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019-2020 NXP
*/
/dts-v1/;
#include "imx8mm-evk.dtsi"
/ {
model = "FSL i.MX8MM EVKB";
compatible = "fsl,imx8mm-evkb", "fsl,imx8mm";
};
&i2c1 {
/delete-node/ pmic@4b;
pmic@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
/* VDD_SOC with PCIe */
buck1_reg: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* VDD_ARM */
buck2_reg: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-standby-voltage = <850000>;
};
/* VDD_GPU, VDD_VPU, VDD_DRAM */
buck3_reg: BUCK3 {
regulator-name = "BUCK3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
/* NVCC_3V3 */
buck4_reg: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1V8, NVCC_1V8, NVCC_ENET */
buck5_reg: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* NVCC_DRAM for LPDDR4 */
buck6_reg: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
/* NVCC_SNVS_1P8 */
ldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_SNVS_0P8 */
ldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_*_1V8 */
ldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_PHY_0V9 */
ldo4_reg: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* NVCC_SD2 */
ldo5_reg: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};

87
arch/arm64/boot/dts/freescale/imx8mm-phg.dts
View File

@ -80,6 +80,35 @@
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
panel {
compatible = "panel-lvds";
width-mm = <170>;
height-mm = <28>;
data-mapping = "jeida-18";
panel-timing {
clock-frequency = <49500000>;
hactive = <800>;
hback-porch = <48>;
hfront-porch = <312>;
hsync-len = <40>;
vactive = <600>;
vback-porch = <19>;
vfront-porch = <61>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
port {
panel_out_bridge: endpoint {
remote-endpoint = <&bridge_out_panel>;
};
};
};
};
&ecspi1 {
@ -113,8 +142,60 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
bridge@2c {
compatible = "ti,sn65dsi83";
reg = <0x2c>;
enable-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dsi_bridge>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in_dsi: endpoint {
remote-endpoint = <&dsi_out_bridge>;
data-lanes = <1 2 3 4>;
};
};
port@2 {
reg = <2>;
bridge_out_panel: endpoint {
remote-endpoint = <&panel_out_bridge>;
};
};
};
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
ports {
port@1 {
reg = <1>;
dsi_out_bridge: endpoint {
data-lanes = <1 2>;
lane-polarities = <1 0 0 0 0>;
remote-endpoint = <&bridge_in_dsi>;
};
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@ -166,6 +247,12 @@
>;
};
pinctrl_dsi_bridge: dsibridgeggrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x19
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82

2
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
View File

@ -219,12 +219,14 @@
read-only;
reg = <0x53>;
pagesize = <16>;
vcc-supply = <&reg_vcc3v3>;
};
eeprom0: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_vcc3v3>;
};
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
View File

@ -149,7 +149,7 @@
};
channel@8 {
gw,mode = <1>;
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
@ -234,8 +234,6 @@
};
fan-controller@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "gw,gsc-fan";
reg = <0x0a>;
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@ -354,7 +354,7 @@
};
channel@8 {
gw,mode = <1>;
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@ -327,7 +327,7 @@
};
channel@8 {
gw,mode = <1>;
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@ -293,7 +293,7 @@
};
channel@8 {
gw,mode = <1>;
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};

103
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
View File

@ -43,6 +43,17 @@
enable-active-high;
};
reg_camera: regulator-camera {
compatible = "regulator-fixed";
regulator-name = "mipi_pwr";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "vsd_3v3";
@ -63,18 +74,30 @@
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
sound-wm8962 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8962";
simple-audio-card,format = "i2s";
simple-audio-card,widgets = "Headphone", "Headphones",
"Microphone", "Headset Mic",
"Speaker", "Speaker";
simple-audio-card,routing = "Headphones", "HPOUTL",
"Headphones", "HPOUTR",
"Speaker", "SPKOUTL",
"Speaker", "SPKOUTR",
"Headset Mic", "MICBIAS",
"IN3R", "Headset Mic";
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
frame-master;
bitclock-master;
};
};
};
@ -96,6 +119,36 @@
};
};
&i2c2 {
clock-frequency = <384000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
camera@10 {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x10>;
clocks = <&clk IMX8MN_CLK_CLKO1>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
assigned-clock-rates = <24000000>;
AVDD-supply = <&reg_camera>; /* 2.8v */
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
port {
/* MIPI CSI-2 bus endpoint */
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -142,14 +195,32 @@
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
#sound-dai-cells = <0>;
};
};
&isi {
status = "okay";
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&mipi_csi {
status = "okay";
ports {
port@0 {
mipi_csi_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -226,6 +297,14 @@
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19

40
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
View File

@ -152,46 +152,6 @@
extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};
&pinctrl_fec1 {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&pinctrl_fec1_sleep {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <

7
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@ -27,6 +27,7 @@
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@ -222,6 +223,12 @@
};
};
};
eeprom_som: eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c3 {

2
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
View File

@ -325,7 +325,7 @@
};
channel@8 {
gw,mode = <1>;
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};

60
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -1117,6 +1117,30 @@
};
};
isi: isi@32e20000 {
compatible = "fsl,imx8mn-isi";
reg = <0x32e20000 0x8000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
clock-names = "axi", "apb";
fsl,blk-ctrl = <&disp_blk_ctrl>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in: endpoint {
remote-endpoint = <&mipi_csi_out>;
};
};
};
};
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
@ -1145,6 +1169,42 @@
#power-domain-cells = <1>;
};
mipi_csi: mipi-csi@32e30000 {
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
<&clk IMX8MN_CLK_CSI1_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_CAMERA_PIXEL>,
<&clk IMX8MN_CLK_CSI1_PHY_REF>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_out: endpoint {
remote-endpoint = <&isi_in>;
};
};
};
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x32e40000 0x200>;

89
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View File

@ -118,6 +118,15 @@
clock-frequency = <100000000>;
};
reg_audio: regulator-wm8962 {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@ -137,6 +146,32 @@
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound-wm8962 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8962";
simple-audio-card,format = "i2s";
simple-audio-card,widgets = "Headphone", "Headphones",
"Microphone", "Headset Mic",
"Speaker", "Speaker";
simple-audio-card,routing = "Headphones", "HPOUTL",
"Headphones", "HPOUTR",
"Speaker", "SPKOUTL",
"Speaker", "SPKOUTR",
"Headset Mic", "MICBIAS",
"IN3R", "Headset Mic";
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
frame-master;
bitclock-master;
};
};
};
&ecspi2 {
@ -239,6 +274,34 @@
clock-frequency = <384000>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <22576000>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
#sound-dai-cells = <0>;
};
pca6416: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
@ -315,6 +378,16 @@
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -477,6 +550,16 @@
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
@ -547,4 +630,10 @@
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_wm8962: wm8962grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59
>;
};
};

54
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
View File

@ -23,6 +23,12 @@
stdout-path = &uart1;
};
clk_ext_audio_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
gpio-keys {
compatible = "gpio-keys";
@ -102,6 +108,43 @@
pinctrl-names = "default";
};
};
reg_3p3vdd: regulator-3p3vdd { /* 3.3VDD */
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "3P3VDD";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SGTL5000-Card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,widgets = "Headphone", "Headphone Jack";
simple-audio-card,routing = "Headphone Jack", "HP_OUT";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&sai3>;
};
codec_dai: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
};
&i2c5 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
VDDA-supply = <&reg_3p3vdd>;
VDDIO-supply = <&reg_vdd_3p3v_awo>;
};
};
&fec { /* Second ethernet */
@ -155,6 +198,17 @@
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usb3_1 {
fsl,over-current-active-low;
};

60
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
View File

@ -23,10 +23,16 @@
stdout-path = &uart1;
};
clk_pcie: clock-pcie {
clk_ext_audio_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-frequency = <24000000>;
};
clk_xtal25: clock-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
connector {
@ -140,12 +146,30 @@
};
};
reg_avdd: regulator-avdd { /* AUDIO_VDD */
reg_3p3vdd: regulator-3p3vdd { /* 3.3VDD */
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "AUDIO_VDD";
regulator-name = "3P3VDD";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SGTL5000-Card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,widgets = "Headphone", "Headphone Jack";
simple-audio-card,routing = "Headphone Jack", "HP_OUT";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&sai3>;
};
codec_dai: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
};
@ -161,6 +185,15 @@
#size-cells = <0>;
reg = <0>;
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
VDDA-supply = <&reg_3p3vdd>;
VDDIO-supply = <&reg_vdd_3p3v_awo>;
};
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
@ -203,6 +236,13 @@
pagesize = <16>;
reg = <0x54>;
};
pcieclk: clock@6b {
compatible = "skyworks,si52144";
reg = <0x6b>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
i2cmuxed1: i2c@1 { /* HDMI DDC I2C */
@ -244,7 +284,7 @@
};
&pcie_phy {
clocks = <&clk_pcie>;
clocks = <&pcieclk 1>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
@ -256,6 +296,16 @@
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usb_dwc3_0 {
usb-role-switch;

72
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -49,6 +49,14 @@
startup-delay-us = <100>;
vin-supply = <&buck4>;
};
reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VDD_3P3V_AWO";
};
};
&A53_0 {
@ -232,6 +240,36 @@
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
tc_bridge: bridge@f {
compatible = "toshiba,tc9595", "toshiba,tc358767";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tc9595>;
reg = <0xf>;
clock-names = "ref";
clocks = <&clk IMX8MP_CLK_CLKOUT2>;
assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
<&clk IMX8MP_CLK_CLKOUT2>,
<&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <13000000>, <13000000>, <156000000>;
reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tc_bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&dsi_out>;
};
};
};
};
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
@ -398,6 +436,22 @@
status = "okay";
};
&mipi_dsi {
samsung,burst-clock-frequency = <160000000>;
samsung,esc-clock-frequency = <10000000>;
ports {
port@1 {
reg = <1>;
dsi_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&tc_bridge_in>;
};
};
};
};
&pwm1 {
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";
@ -863,6 +917,24 @@
>;
};
pinctrl_tc9595: dhcom-tc9595-grp {
fsl,pins = <
/* RESET_DSIBRIDGE */
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146
/* DSI-CONV_INT Interrupt */
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141
>;
};
pinctrl_sai3: dhcom-sai3-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
>;
};
pinctrl_touch: dhcom-touch-grp {
fsl,pins = <
/* #TOUCH_INT */

80
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -40,6 +40,17 @@
clock-frequency = <100000000>;
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_pwr_reg>;
regulator-name = "audio-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
@ -83,6 +94,37 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8960-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Speaker", "External Speaker",
"Microphone", "Mic Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"External Speaker", "SPK_LP",
"External Speaker", "SPK_LN",
"External Speaker", "SPK_RP",
"External Speaker", "SPK_RN",
"LINPUT1", "Mic Jack",
"LINPUT3", "Mic Jack",
"Mic Jack", "MICB";
cpudai: simple-audio-card,cpu {
sound-dai = <&sai3>;
};
simple-audio-card,codec {
sound-dai = <&wm8960>;
};
};
};
&flexspi {
@ -344,6 +386,18 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
clock-names = "mclk";
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
SPKVDD1-supply = <&reg_audio_pwr>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
@ -422,6 +476,16 @@
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -499,6 +563,12 @@
};
&iomuxc {
pinctrl_audio_pwr_reg: audiopwrreggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
@ -668,6 +738,16 @@
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140

70
arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
View File

@ -14,6 +14,67 @@
compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
"avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
"fsl,imx8mp";
reg_vcc_3v3_audio: 3v3-audio-regulator {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_AUD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vcc_1v8_audio: 1v8-audio-regulator {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8_AUD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sgtl5000-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
codec_dai: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
};
&i2c1 {
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
clocks = <&clk IMX8MP_CLK_CLKOUT1>;
clock-names = "mclk";
#sound-dai-cells = <0>;
VDDA-supply = <&reg_vcc_3v3_audio>;
VDDD-supply = <&reg_vcc_1v8_audio>;
VDDIO-supply = <&reg_vcc_1v8_audio>;
};
};
/* I2S-0 = sai2 */
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&flexcan1 {
@ -32,6 +93,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_smarc_gpio>;
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
>;
};
pinctrl_smarc_gpio: smarcgpiosgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x19>, /* GPIO0 */

46
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@ -202,6 +202,13 @@
};
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tq-tlv320aic32x";
audio-cpu = <&sai3>;
audio-codec = <&tlv320aic3x04>;
};
thermal-zones {
soc-thermal {
trips {
@ -449,6 +456,18 @@
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tlv320aic3x04>;
reg = <0x18>;
clock-names = "mclk";
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
iov-supply = <&reg_vcc_3v3>;
ldoin-supply = <&reg_vcc_3v3>;
};
se97_1c: temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
@ -528,6 +547,16 @@
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -843,6 +872,23 @@
fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94
>;
};
pinctrl_tlv320aic3x04: tlv320aic3x04grp {
fsl,pins = <
/* CODEC RST# */
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180
>;
};
/* X61 */
pinctrl_uart1: uart1grp {
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>,

587
arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi Normal file
View File

@ -0,0 +1,587 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
aliases {
ethernet0 = &eqos;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
};
&A53_0 {
cpu-supply = <&buck3_reg>;
};
&A53_1 {
cpu-supply = <&buck3_reg>;
};
&A53_2 {
cpu-supply = <&buck3_reg>;
};
&A53_3 {
cpu-supply = <&buck3_reg>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <0x0>;
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
channel@16 {
gw,mode = <4>;
reg = <0x16>;
label = "fan_tach";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_adc1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_adc2";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_1p0";
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_1p8";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_2p5";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_dram";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_soc";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_arm";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
fan-controller@0 {
compatible = "gw,gsc-fan";
reg = <0x0a>;
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
pmic@69 {
compatible = "mps,mp5416";
reg = <0x69>;
regulators {
/* vdd_soc */
buck1 {
regulator-name = "buck1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
/* vdd_dram */
buck2 {
regulator-name = "buck2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
/* vdd_arm */
buck3_reg: buck3 {
regulator-name = "buck3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
/* vdd_1p8 */
buck4 {
regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT2: nvcc_snvs_1p8 */
ldo1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT3: vdd_1p0 */
ldo2 {
regulator-name = "ldo2";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT4: vdd_2p5 */
ldo3 {
regulator-name = "ldo3";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT5: vdd_3p3 */
ldo4 {
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
/* off-board header */
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* off-board */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
non-removable;
status = "okay";
bus-width = <4>;
non-removable;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@ -281,7 +281,7 @@
};
channel@8 {
gw,mode = <1>;
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};

28
arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mp.dtsi"
#include "imx8mp-venice-gw702x.dtsi"
#include "imx8mp-venice-gw7905.dtsi"
/ {
model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit";
compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
};
/* Disable SOM interfaces not used on baseboard */
&eqos {
status = "disabled";
};
&usdhc1 {
status = "disabled";
};

309
arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi Normal file
View File

@ -0,0 +1,309 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_usb2_vbus: regulator-usb2-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
compatible = "regulator-fixed";
regulator-name = "SD2_3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpio4 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "gpioa", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "gpiod", "", "",
"gpiob", "gpioc", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "pci_usb_sel", "",
"pci_wdis#", "", "", "";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* USB1 - Type C front panel SINK port J14 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "peripheral";
status = "okay";
};
/* USB2 4-port USB3.0 HUB:
* P1 - USBC connector (host only)
* P2 - USB2 test connector
* P3 - miniPCIe full card
* P4 - miniPCIe half card
*/
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */
MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */
MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
};

490
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -304,6 +304,210 @@
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
etm0: etm@28440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28440000 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_0>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
etm1: etm@28540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28540000 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_1>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
etm2: etm@28640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28640000 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_2>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port2>;
};
};
};
};
etm3: etm@28740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x28740000 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_3>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port3>;
};
};
};
};
funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
funnel@28c03000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x28c03000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
remote-endpoint = <&ca_funnel_out_port0>;
};
};
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
/* M7 input */
};
};
port@2 {
reg = <2>;
hugo_funnel_in_port2: endpoint {
/* DSP input */
};
};
/* the other input ports are not connect to anything */
};
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
};
};
etf@28c04000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x28c04000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
port {
etf_in_port: endpoint {
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
};
etr@28c06000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x28c06000 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&etf_out_port>;
};
};
};
};
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
@ -534,26 +738,16 @@
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
<&clk IMX8MP_CLK_GIC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
<&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
<500000000>,
<400000000>,
<800000000>,
<393216000>,
<361267200>;
<500000000>;
};
src: reset-controller@30390000 {
@ -595,6 +789,13 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
pgc_audio: power-domain@5 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AXI>;
};
pgc_gpu2d: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@ -1147,6 +1348,157 @@
};
};
aips5: bus@30c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
spba-bus@30c00000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sai1: sai@30c10000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c10000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai2: sai@30c20000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c20000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai3: sai@30c30000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c30000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai5: sai@30c50000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c50000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai6: sai@30c60000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c60000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sai7: sai@30c80000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
reg = <0x30c80000 0x10000>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
dma-names = "rx", "tx";
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e00000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
sdma2: dma-controller@30e10000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e10000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
audio_blk_ctrl: clock-controller@30e20000 {
compatible = "fsl,imx8mp-audio-blk-ctrl";
reg = <0x30e20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_SAI1>,
<&clk IMX8MP_CLK_SAI2>,
<&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_CLK_SAI5>,
<&clk IMX8MP_CLK_SAI6>,
<&clk IMX8MP_CLK_SAI7>;
clock-names = "ahb",
"sai1", "sai2", "sai3",
"sai5", "sai6", "sai7";
power-domains = <&pgc_audio>;
};
};
noc: interconnect@32700000 {
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
reg = <0x32700000 0x100000>;
@ -1174,6 +1526,118 @@
#size-cells = <1>;
ranges;
isi_0: isi@32e00000 {
compatible = "fsl,imx8mp-isi";
reg = <0x32e00000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "apb";
fsl,blk-ctrl = <&media_blk_ctrl>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in_0: endpoint {
remote-endpoint = <&mipi_csi_0_out>;
};
};
port@1 {
reg = <1>;
isi_in_1: endpoint {
remote-endpoint = <&mipi_csi_1_out>;
};
};
};
};
dewarp: dwe@32e30000 {
compatible = "nxp,imx8mp-dw100";
reg = <0x32e30000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "axi", "ahb";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
};
mipi_csi_0: csi@32e40000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_0_out: endpoint {
remote-endpoint = <&isi_in_0>;
};
};
};
};
mipi_csi_1: csi@32e50000 {
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_1_out: endpoint {
remote-endpoint = <&isi_in_1>;
};
};
};
};
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;

2
arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
View File

@ -26,7 +26,7 @@
};
panel {
compatible = "innolux,n125hce-gn1", "simple-panel";
compatible = "innolux,n125hce-gn1";
power-supply = <&reg_main_3v3>;
backlight = <&backlight>;
no-hpd;

4
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
View File

@ -108,8 +108,6 @@
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
epdev_on-supply = <&reg_vcc_3v3>;
hard-wired = <1>;
status = "okay";
};
@ -122,8 +120,6 @@
<&pcie1_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
epdev_on-supply = <&reg_vcc_3v3>;
hard-wired = <1>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@ -177,7 +177,7 @@
port@2 {
reg = <2>;
label = "cpu";
phy-mode = "rev-rmii";
ethernet = <&fec1>;
fixed-link {

13
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -547,11 +547,13 @@
};
lcdif: lcd-controller@30320000 {
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";
reg = <0x30320000 0x10000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
clock-names = "pix";
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
<&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_CLK_LCDIF_PIXEL>,
@ -1054,9 +1056,11 @@
};
};
mipi_dsi: mipi-dsi@30a00000 {
mipi_dsi: dsi@30a00000 {
compatible = "fsl,imx8mq-nwl-dsi";
reg = <0x30a00000 0x300>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_AHB>,
<&clk IMX8MQ_CLK_DSI_IPG_DIV>,
@ -1577,6 +1581,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;

1
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -52,6 +52,7 @@
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@ -116,6 +116,10 @@
no-mmc;
};
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <

135
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -46,12 +46,27 @@
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <10000>;
exit-latency-us = <7000>;
min-residency-us = <27000>;
wakeup-latency-us = <15000>;
};
};
A55_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A55_1: cpu@100 {
@ -60,6 +75,7 @@
reg = <0x100>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
};
@ -153,6 +169,24 @@
nxp,no-divider;
};
wdog1: watchdog@442d0000 {
compatible = "fsl,imx93-wdt";
reg = <0x442d0000 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WDOG1_GATE>;
timeout-sec = <40>;
status = "disabled";
};
wdog2: watchdog@442e0000 {
compatible = "fsl,imx93-wdt";
reg = <0x442e0000 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WDOG2_GATE>;
timeout-sec = <40>;
status = "disabled";
};
tpm1: pwm@44310000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x44310000 0x1000>;
@ -287,14 +321,6 @@
#size-cells = <1>;
ranges;
mediamix: power-domain@44462400 {
compatible = "fsl,imx93-src-slice";
reg = <0x44462400 0x400>, <0x44465800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>;
};
mlmix: power-domain@44461800 {
compatible = "fsl,imx93-src-slice";
reg = <0x44461800 0x400>, <0x44464800 0x400>;
@ -302,6 +328,14 @@
clocks = <&clk IMX93_CLK_ML_APB>,
<&clk IMX93_CLK_ML>;
};
mediamix: power-domain@44462400 {
compatible = "fsl,imx93-src-slice";
reg = <0x44462400 0x400>, <0x44465800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>;
};
};
anatop: anatop@44480000 {
@ -344,6 +378,33 @@
status = "disabled";
};
wdog3: watchdog@42490000 {
compatible = "fsl,imx93-wdt";
reg = <0x42490000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WDOG3_GATE>;
timeout-sec = <40>;
status = "disabled";
};
wdog4: watchdog@424a0000 {
compatible = "fsl,imx93-wdt";
reg = <0x424a0000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WDOG4_GATE>;
timeout-sec = <40>;
status = "disabled";
};
wdog5: watchdog@424b0000 {
compatible = "fsl,imx93-wdt";
reg = <0x424b0000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WDOG5_GATE>;
timeout-sec = <40>;
status = "disabled";
};
tpm3: pwm@424e0000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x424e0000 0x1000>;
@ -640,28 +701,6 @@
status = "disabled";
};
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_ENET_QOS_GATE>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
status = "disabled";
};
fec: ethernet@42890000 {
compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x42890000 0x10000>;
@ -685,6 +724,29 @@
assigned-clock-rates = <100000000>, <250000000>, <50000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
status = "disabled";
};
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_ENET_QOS_GATE>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
status = "disabled";
};
@ -760,6 +822,13 @@
gpio-ranges = <&iomuxc 0 92 16>;
};
ocotp: efuse@47510000 {
compatible = "fsl,imx93-ocotp", "syscon";
reg = <0x47510000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
s4muap: mailbox@47520000 {
compatible = "fsl,imx93-mu-s4";
reg = <0x47520000 0x10000>;
@ -788,5 +857,11 @@
#power-domain-cells = <1>;
status = "disabled";
};
ddr-pmu@4e300dc0 {
compatible = "fsl,imx93-ddr-pmu";
reg = <0x4e300dc0 0x200>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
};
};
};