mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
drm/i915: refactor skylake scaler code into new file.
This moves the code from various places and consolidates it into one new file. v2: - rename skl_program_plane -> skl_program_plane_scaler (Ville) - also move skl_pfit_enable, and consequently make some skl_scaler_* functions static to skl_scaler.c (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2fa703ffc7b96a41c392fd5ebbd2e6e4ffb6fb05.1612536383.git.jani.nikula@intel.com
This commit is contained in:
parent
2a3014490c
commit
714b1cdb02
14 changed files with 598 additions and 564 deletions
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@ -224,6 +224,7 @@ i915-y += \
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display/intel_tc.o \
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display/intel_vga.o \
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display/i9xx_plane.o \
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display/skl_scaler.o \
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display/skl_universal_plane.o
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i915-$(CONFIG_ACPI) += \
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display/intel_acpi.o \
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@ -35,6 +35,7 @@
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#include "intel_dsi.h"
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#include "intel_panel.h"
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#include "intel_vdsc.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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static int header_credits_available(struct drm_i915_private *dev_priv,
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@ -40,7 +40,7 @@
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#include "intel_global_state.h"
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#include "intel_hdcp.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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#include "skl_universal_plane.h"
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/**
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* intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
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@ -54,6 +54,7 @@
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#include "intel_tc.h"
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#include "intel_vdsc.h"
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#include "intel_vrr.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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static const u8 index_to_dp_signal_levels[] = {
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@ -94,6 +94,7 @@
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#include "intel_tc.h"
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#include "intel_vga.h"
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#include "i9xx_plane.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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@ -2524,38 +2525,6 @@ intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
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return y;
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}
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static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
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intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
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intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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/*
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* This function detaches (aka. unbinds) unused scalers in hardware
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*/
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static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
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const struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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int i;
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/* loop through and disable scalers that aren't in use */
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for (i = 0; i < intel_crtc->num_scalers; i++) {
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if (!scaler_state->scalers[i].in_use)
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skl_detach_scaler(intel_crtc, i);
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}
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}
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static int
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__intel_display_resume(struct drm_device *dev,
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struct drm_atomic_state *state,
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@ -3120,461 +3089,6 @@ static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
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}
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}
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/*
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* The hardware phase 0.0 refers to the center of the pixel.
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* We want to start from the top/left edge which is phase
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* -0.5. That matches how the hardware calculates the scaling
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* factors (from top-left of the first pixel to bottom-right
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* of the last pixel, as opposed to the pixel centers).
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*
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* For 4:2:0 subsampled chroma planes we obviously have to
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* adjust that so that the chroma sample position lands in
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* the right spot.
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*
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* Note that for packed YCbCr 4:2:2 formats there is no way to
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* control chroma siting. The hardware simply replicates the
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* chroma samples for both of the luma samples, and thus we don't
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* actually get the expected MPEG2 chroma siting convention :(
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* The same behaviour is observed on pre-SKL platforms as well.
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*
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* Theory behind the formula (note that we ignore sub-pixel
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* source coordinates):
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* s = source sample position
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* d = destination sample position
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*
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* Downscaling 4:1:
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* -0.5
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* | 0.0
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* | | 1.5 (initial phase)
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* | | |
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* v v v
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* | s | s | s | s |
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* | d |
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*
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* Upscaling 1:4:
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* -0.5
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* | -0.375 (initial phase)
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* | | 0.0
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* | | |
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* v v v
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* | s |
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* | d | d | d | d |
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*/
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
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{
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int phase = -0x8000;
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u16 trip = 0;
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if (chroma_cosited)
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phase += (sub - 1) * 0x8000 / sub;
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phase += scale / (2 * sub);
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/*
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* Hardware initial phase limited to [-0.5:1.5].
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* Since the max hardware scale factor is 3.0, we
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* should never actually excdeed 1.0 here.
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*/
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WARN_ON(phase < -0x8000 || phase > 0x18000);
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if (phase < 0)
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phase = 0x10000 + phase;
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else
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trip = PS_PHASE_TRIP;
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return ((phase >> 2) & PS_PHASE_MASK) | trip;
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}
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#define SKL_MIN_SRC_W 8
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#define SKL_MAX_SRC_W 4096
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#define SKL_MIN_SRC_H 8
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#define SKL_MAX_SRC_H 4096
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#define SKL_MIN_DST_W 8
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#define SKL_MAX_DST_W 4096
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#define SKL_MIN_DST_H 8
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#define SKL_MAX_DST_H 4096
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#define ICL_MAX_SRC_W 5120
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#define ICL_MAX_SRC_H 4096
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#define ICL_MAX_DST_W 5120
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#define ICL_MAX_DST_H 4096
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#define SKL_MIN_YUV_420_SRC_W 16
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#define SKL_MIN_YUV_420_SRC_H 16
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static int
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skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
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unsigned int scaler_user, int *scaler_id,
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int src_w, int src_h, int dst_w, int dst_h,
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const struct drm_format_info *format,
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u64 modifier, bool need_scaler)
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{
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struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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struct intel_crtc *intel_crtc =
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to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->hw.adjusted_mode;
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/*
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* Src coordinates are already rotated by 270 degrees for
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* the 90/270 degree plane rotation cases (to match the
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* GTT mapping), hence no need to account for rotation here.
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*/
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if (src_w != dst_w || src_h != dst_h)
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need_scaler = true;
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/*
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* Scaling/fitting not supported in IF-ID mode in GEN9+
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* TODO: Interlace fetch mode doesn't support YUV420 planar formats.
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* Once NV12 is enabled, handle it here while allocating scaler
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* for NV12.
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*/
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if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
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need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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drm_dbg_kms(&dev_priv->drm,
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"Pipe/Plane scaling not supported with IF-ID mode\n");
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return -EINVAL;
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}
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/*
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* if plane is being disabled or scaler is no more required or force detach
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* - free scaler binded to this plane/crtc
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* - in order to do this, update crtc->scaler_usage
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*
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* Here scaler state in crtc_state is set free so that
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* scaler can be assigned to other user. Actual register
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* update to free the scaler is done in plane/panel-fit programming.
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* For this purpose crtc/plane_state->scaler_id isn't reset here.
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*/
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if (force_detach || !need_scaler) {
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if (*scaler_id >= 0) {
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scaler_state->scaler_users &= ~(1 << scaler_user);
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scaler_state->scalers[*scaler_id].in_use = 0;
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drm_dbg_kms(&dev_priv->drm,
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"scaler_user index %u.%u: "
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"Staged freeing scaler id %d scaler_users = 0x%x\n",
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intel_crtc->pipe, scaler_user, *scaler_id,
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scaler_state->scaler_users);
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*scaler_id = -1;
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}
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return 0;
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}
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if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
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(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
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drm_dbg_kms(&dev_priv->drm,
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"Planar YUV: src dimensions not met\n");
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return -EINVAL;
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}
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/* range checks */
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if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
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dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
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(INTEL_GEN(dev_priv) >= 11 &&
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(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
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dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
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(INTEL_GEN(dev_priv) < 11 &&
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(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
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dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
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drm_dbg_kms(&dev_priv->drm,
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"scaler_user index %u.%u: src %ux%u dst %ux%u "
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"size is out of scaler range\n",
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intel_crtc->pipe, scaler_user, src_w, src_h,
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dst_w, dst_h);
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return -EINVAL;
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}
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/* mark this plane as a scaler user in crtc_state */
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scaler_state->scaler_users |= (1 << scaler_user);
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drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
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"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
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intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
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scaler_state->scaler_users);
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return 0;
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}
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static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
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{
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const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
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int width, height;
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if (crtc_state->pch_pfit.enabled) {
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width = drm_rect_width(&crtc_state->pch_pfit.dst);
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height = drm_rect_height(&crtc_state->pch_pfit.dst);
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} else {
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width = pipe_mode->crtc_hdisplay;
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height = pipe_mode->crtc_vdisplay;
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}
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return skl_update_scaler(crtc_state, !crtc_state->hw.active,
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SKL_CRTC_INDEX,
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&crtc_state->scaler_state.scaler_id,
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crtc_state->pipe_src_w, crtc_state->pipe_src_h,
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width, height, NULL, 0,
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crtc_state->pch_pfit.enabled);
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}
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/**
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* skl_update_scaler_plane - Stages update to scaler state for a given plane.
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* @crtc_state: crtc's scaler state
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* @plane_state: atomic plane state to update
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*
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* Return
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* 0 - scaler_usage updated successfully
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* error - requested scaling cannot be supported or other error condition
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*/
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static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state)
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{
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struct intel_plane *intel_plane =
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to_intel_plane(plane_state->uapi.plane);
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struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
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struct drm_framebuffer *fb = plane_state->hw.fb;
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int ret;
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bool force_detach = !fb || !plane_state->uapi.visible;
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bool need_scaler = false;
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/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
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if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
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fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
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need_scaler = true;
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ret = skl_update_scaler(crtc_state, force_detach,
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drm_plane_index(&intel_plane->base),
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&plane_state->scaler_id,
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drm_rect_width(&plane_state->uapi.src) >> 16,
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drm_rect_height(&plane_state->uapi.src) >> 16,
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drm_rect_width(&plane_state->uapi.dst),
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drm_rect_height(&plane_state->uapi.dst),
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fb ? fb->format : NULL,
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fb ? fb->modifier : 0,
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need_scaler);
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if (ret || plane_state->scaler_id < 0)
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return ret;
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/* check colorkey */
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if (plane_state->ckey.flags) {
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drm_dbg_kms(&dev_priv->drm,
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"[PLANE:%d:%s] scaling with color key not allowed",
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intel_plane->base.base.id,
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intel_plane->base.name);
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return -EINVAL;
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}
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/* Check src format */
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switch (fb->format->format) {
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XRGB2101010:
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case DRM_FORMAT_XBGR2101010:
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_ABGR2101010:
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_YVYU:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_VYUY:
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_XYUV8888:
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case DRM_FORMAT_P010:
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case DRM_FORMAT_P012:
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case DRM_FORMAT_P016:
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case DRM_FORMAT_Y210:
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case DRM_FORMAT_Y212:
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case DRM_FORMAT_Y216:
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case DRM_FORMAT_XVYU2101010:
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case DRM_FORMAT_XVYU12_16161616:
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case DRM_FORMAT_XVYU16161616:
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break;
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case DRM_FORMAT_XBGR16161616F:
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case DRM_FORMAT_ABGR16161616F:
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case DRM_FORMAT_XRGB16161616F:
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case DRM_FORMAT_ARGB16161616F:
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if (INTEL_GEN(dev_priv) >= 11)
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break;
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fallthrough;
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default:
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drm_dbg_kms(&dev_priv->drm,
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"[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
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intel_plane->base.base.id, intel_plane->base.name,
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fb->base.id, fb->format->format);
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return -EINVAL;
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}
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return 0;
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}
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void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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int i;
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for (i = 0; i < crtc->num_scalers; i++)
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skl_detach_scaler(crtc, i);
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}
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static int cnl_coef_tap(int i)
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{
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return i % 7;
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}
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static u16 cnl_nearest_filter_coef(int t)
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{
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return t == 3 ? 0x0800 : 0x3000;
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}
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/*
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* Theory behind setting nearest-neighbor integer scaling:
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*
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* 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
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* The letter represents the filter tap (D is the center tap) and the number
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* represents the coefficient set for a phase (0-16).
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*
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* +------------+------------------------+------------------------+
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* |Index value | Data value coeffient 1 | Data value coeffient 2 |
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* +------------+------------------------+------------------------+
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* | 00h | B0 | A0 |
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* +------------+------------------------+------------------------+
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* | 01h | D0 | C0 |
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* +------------+------------------------+------------------------+
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* | 02h | F0 | E0 |
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* +------------+------------------------+------------------------+
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* | 03h | A1 | G0 |
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* +------------+------------------------+------------------------+
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* | 04h | C1 | B1 |
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* +------------+------------------------+------------------------+
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* | ... | ... | ... |
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* +------------+------------------------+------------------------+
|
||||
* | 38h | B16 | A16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 39h | D16 | C16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 3Ah | F16 | C16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 3Bh | Reserved | G16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
*
|
||||
* To enable nearest-neighbor scaling: program scaler coefficents with
|
||||
* the center tap (Dxx) values set to 1 and all other values set to 0 as per
|
||||
* SCALER_COEFFICIENT_FORMAT
|
||||
*
|
||||
*/
|
||||
|
||||
static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
|
||||
enum pipe pipe, int id, int set)
|
||||
{
|
||||
int i;
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
|
||||
PS_COEE_INDEX_AUTO_INC);
|
||||
|
||||
for (i = 0; i < 17 * 7; i += 2) {
|
||||
u32 tmp;
|
||||
int t;
|
||||
|
||||
t = cnl_coef_tap(i);
|
||||
tmp = cnl_nearest_filter_coef(t);
|
||||
|
||||
t = cnl_coef_tap(i + 1);
|
||||
tmp |= cnl_nearest_filter_coef(t) << 16;
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
|
||||
tmp);
|
||||
}
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
|
||||
}
|
||||
|
||||
u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
|
||||
{
|
||||
if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
|
||||
return (PS_FILTER_PROGRAMMED |
|
||||
PS_Y_VERT_FILTER_SELECT(set) |
|
||||
PS_Y_HORZ_FILTER_SELECT(set) |
|
||||
PS_UV_VERT_FILTER_SELECT(set) |
|
||||
PS_UV_HORZ_FILTER_SELECT(set));
|
||||
}
|
||||
|
||||
return PS_FILTER_MEDIUM;
|
||||
}
|
||||
|
||||
void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
|
||||
int id, int set, enum drm_scaling_filter filter)
|
||||
{
|
||||
switch (filter) {
|
||||
case DRM_SCALING_FILTER_DEFAULT:
|
||||
break;
|
||||
case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
|
||||
cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
|
||||
break;
|
||||
default:
|
||||
MISSING_CASE(filter);
|
||||
}
|
||||
}
|
||||
|
||||
static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct intel_crtc_scaler_state *scaler_state =
|
||||
&crtc_state->scaler_state;
|
||||
struct drm_rect src = {
|
||||
.x2 = crtc_state->pipe_src_w << 16,
|
||||
.y2 = crtc_state->pipe_src_h << 16,
|
||||
};
|
||||
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
|
||||
u16 uv_rgb_hphase, uv_rgb_vphase;
|
||||
enum pipe pipe = crtc->pipe;
|
||||
int width = drm_rect_width(dst);
|
||||
int height = drm_rect_height(dst);
|
||||
int x = dst->x1;
|
||||
int y = dst->y1;
|
||||
int hscale, vscale;
|
||||
unsigned long irqflags;
|
||||
int id;
|
||||
u32 ps_ctrl;
|
||||
|
||||
if (!crtc_state->pch_pfit.enabled)
|
||||
return;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm,
|
||||
crtc_state->scaler_state.scaler_id < 0))
|
||||
return;
|
||||
|
||||
hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
|
||||
vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
|
||||
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
|
||||
id = scaler_state->scaler_id;
|
||||
|
||||
ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
|
||||
ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
||||
|
||||
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
|
||||
crtc_state->hw.scaling_filter);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
|
||||
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
|
||||
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
|
||||
x << 16 | y);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
|
||||
width << 16 | height);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
|
|
|
@ -618,12 +618,6 @@ enum intel_display_power_domain
|
|||
intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
|
||||
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *crtc_state);
|
||||
|
||||
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
|
||||
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
|
||||
u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set);
|
||||
void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
|
||||
int id, int set, enum drm_scaling_filter filter);
|
||||
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
|
||||
|
||||
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include "intel_dp_mst.h"
|
||||
#include "intel_dpio_phy.h"
|
||||
#include "intel_hdcp.h"
|
||||
#include "skl_scaler.h"
|
||||
|
||||
static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state,
|
||||
|
|
|
@ -138,68 +138,6 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
skl_program_scaler(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
const struct drm_framebuffer *fb = plane_state->hw.fb;
|
||||
enum pipe pipe = plane->pipe;
|
||||
int scaler_id = plane_state->scaler_id;
|
||||
const struct intel_scaler *scaler =
|
||||
&crtc_state->scaler_state.scalers[scaler_id];
|
||||
int crtc_x = plane_state->uapi.dst.x1;
|
||||
int crtc_y = plane_state->uapi.dst.y1;
|
||||
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
|
||||
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
|
||||
u16 y_hphase, uv_rgb_hphase;
|
||||
u16 y_vphase, uv_rgb_vphase;
|
||||
int hscale, vscale;
|
||||
u32 ps_ctrl;
|
||||
|
||||
hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
|
||||
&plane_state->uapi.dst,
|
||||
0, INT_MAX);
|
||||
vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
|
||||
&plane_state->uapi.dst,
|
||||
0, INT_MAX);
|
||||
|
||||
/* TODO: handle sub-pixel coordinates */
|
||||
if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
|
||||
!icl_is_hdr_plane(dev_priv, plane->id)) {
|
||||
y_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
y_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
|
||||
/* MPEG2 chroma siting convention */
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
|
||||
} else {
|
||||
/* not used */
|
||||
y_hphase = 0;
|
||||
y_vphase = 0;
|
||||
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
}
|
||||
|
||||
ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
|
||||
ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
|
||||
|
||||
skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
|
||||
plane_state->hw.scaling_filter);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
|
||||
(crtc_x << 16) | crtc_y);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
|
||||
(crtc_w << 16) | crtc_h);
|
||||
}
|
||||
|
||||
static void i9xx_plane_linear_gamma(u16 gamma[8])
|
||||
{
|
||||
/* The points are not evenly spaced. */
|
||||
|
|
|
@ -45,10 +45,6 @@ static inline u8 icl_hdr_plane_mask(void)
|
|||
BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
|
||||
}
|
||||
|
||||
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
|
||||
enum plane_id plane_id);
|
||||
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
|
||||
|
||||
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state);
|
||||
int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
|
||||
|
@ -56,7 +52,4 @@ int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
|
|||
int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state);
|
||||
|
||||
void skl_program_scaler(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state);
|
||||
#endif /* __INTEL_SPRITE_H__ */
|
||||
|
|
556
drivers/gpu/drm/i915/display/skl_scaler.c
Normal file
556
drivers/gpu/drm/i915/display/skl_scaler.c
Normal file
|
@ -0,0 +1,556 @@
|
|||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
* Copyright © 2020 Intel Corporation
|
||||
*/
|
||||
#include "intel_display_types.h"
|
||||
#include "skl_scaler.h"
|
||||
#include "skl_universal_plane.h"
|
||||
|
||||
/*
|
||||
* The hardware phase 0.0 refers to the center of the pixel.
|
||||
* We want to start from the top/left edge which is phase
|
||||
* -0.5. That matches how the hardware calculates the scaling
|
||||
* factors (from top-left of the first pixel to bottom-right
|
||||
* of the last pixel, as opposed to the pixel centers).
|
||||
*
|
||||
* For 4:2:0 subsampled chroma planes we obviously have to
|
||||
* adjust that so that the chroma sample position lands in
|
||||
* the right spot.
|
||||
*
|
||||
* Note that for packed YCbCr 4:2:2 formats there is no way to
|
||||
* control chroma siting. The hardware simply replicates the
|
||||
* chroma samples for both of the luma samples, and thus we don't
|
||||
* actually get the expected MPEG2 chroma siting convention :(
|
||||
* The same behaviour is observed on pre-SKL platforms as well.
|
||||
*
|
||||
* Theory behind the formula (note that we ignore sub-pixel
|
||||
* source coordinates):
|
||||
* s = source sample position
|
||||
* d = destination sample position
|
||||
*
|
||||
* Downscaling 4:1:
|
||||
* -0.5
|
||||
* | 0.0
|
||||
* | | 1.5 (initial phase)
|
||||
* | | |
|
||||
* v v v
|
||||
* | s | s | s | s |
|
||||
* | d |
|
||||
*
|
||||
* Upscaling 1:4:
|
||||
* -0.5
|
||||
* | -0.375 (initial phase)
|
||||
* | | 0.0
|
||||
* | | |
|
||||
* v v v
|
||||
* | s |
|
||||
* | d | d | d | d |
|
||||
*/
|
||||
static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
|
||||
{
|
||||
int phase = -0x8000;
|
||||
u16 trip = 0;
|
||||
|
||||
if (chroma_cosited)
|
||||
phase += (sub - 1) * 0x8000 / sub;
|
||||
|
||||
phase += scale / (2 * sub);
|
||||
|
||||
/*
|
||||
* Hardware initial phase limited to [-0.5:1.5].
|
||||
* Since the max hardware scale factor is 3.0, we
|
||||
* should never actually excdeed 1.0 here.
|
||||
*/
|
||||
WARN_ON(phase < -0x8000 || phase > 0x18000);
|
||||
|
||||
if (phase < 0)
|
||||
phase = 0x10000 + phase;
|
||||
else
|
||||
trip = PS_PHASE_TRIP;
|
||||
|
||||
return ((phase >> 2) & PS_PHASE_MASK) | trip;
|
||||
}
|
||||
|
||||
#define SKL_MIN_SRC_W 8
|
||||
#define SKL_MAX_SRC_W 4096
|
||||
#define SKL_MIN_SRC_H 8
|
||||
#define SKL_MAX_SRC_H 4096
|
||||
#define SKL_MIN_DST_W 8
|
||||
#define SKL_MAX_DST_W 4096
|
||||
#define SKL_MIN_DST_H 8
|
||||
#define SKL_MAX_DST_H 4096
|
||||
#define ICL_MAX_SRC_W 5120
|
||||
#define ICL_MAX_SRC_H 4096
|
||||
#define ICL_MAX_DST_W 5120
|
||||
#define ICL_MAX_DST_H 4096
|
||||
#define SKL_MIN_YUV_420_SRC_W 16
|
||||
#define SKL_MIN_YUV_420_SRC_H 16
|
||||
|
||||
static int
|
||||
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
|
||||
unsigned int scaler_user, int *scaler_id,
|
||||
int src_w, int src_h, int dst_w, int dst_h,
|
||||
const struct drm_format_info *format,
|
||||
u64 modifier, bool need_scaler)
|
||||
{
|
||||
struct intel_crtc_scaler_state *scaler_state =
|
||||
&crtc_state->scaler_state;
|
||||
struct intel_crtc *intel_crtc =
|
||||
to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
|
||||
/*
|
||||
* Src coordinates are already rotated by 270 degrees for
|
||||
* the 90/270 degree plane rotation cases (to match the
|
||||
* GTT mapping), hence no need to account for rotation here.
|
||||
*/
|
||||
if (src_w != dst_w || src_h != dst_h)
|
||||
need_scaler = true;
|
||||
|
||||
/*
|
||||
* Scaling/fitting not supported in IF-ID mode in GEN9+
|
||||
* TODO: Interlace fetch mode doesn't support YUV420 planar formats.
|
||||
* Once NV12 is enabled, handle it here while allocating scaler
|
||||
* for NV12.
|
||||
*/
|
||||
if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
|
||||
need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Pipe/Plane scaling not supported with IF-ID mode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* if plane is being disabled or scaler is no more required or force detach
|
||||
* - free scaler binded to this plane/crtc
|
||||
* - in order to do this, update crtc->scaler_usage
|
||||
*
|
||||
* Here scaler state in crtc_state is set free so that
|
||||
* scaler can be assigned to other user. Actual register
|
||||
* update to free the scaler is done in plane/panel-fit programming.
|
||||
* For this purpose crtc/plane_state->scaler_id isn't reset here.
|
||||
*/
|
||||
if (force_detach || !need_scaler) {
|
||||
if (*scaler_id >= 0) {
|
||||
scaler_state->scaler_users &= ~(1 << scaler_user);
|
||||
scaler_state->scalers[*scaler_id].in_use = 0;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"scaler_user index %u.%u: "
|
||||
"Staged freeing scaler id %d scaler_users = 0x%x\n",
|
||||
intel_crtc->pipe, scaler_user, *scaler_id,
|
||||
scaler_state->scaler_users);
|
||||
*scaler_id = -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
|
||||
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Planar YUV: src dimensions not met\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* range checks */
|
||||
if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
|
||||
dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
|
||||
(INTEL_GEN(dev_priv) >= 11 &&
|
||||
(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
|
||||
dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
|
||||
(INTEL_GEN(dev_priv) < 11 &&
|
||||
(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
|
||||
dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"scaler_user index %u.%u: src %ux%u dst %ux%u "
|
||||
"size is out of scaler range\n",
|
||||
intel_crtc->pipe, scaler_user, src_w, src_h,
|
||||
dst_w, dst_h);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* mark this plane as a scaler user in crtc_state */
|
||||
scaler_state->scaler_users |= (1 << scaler_user);
|
||||
drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
|
||||
"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
|
||||
intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
|
||||
scaler_state->scaler_users);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
|
||||
int width, height;
|
||||
|
||||
if (crtc_state->pch_pfit.enabled) {
|
||||
width = drm_rect_width(&crtc_state->pch_pfit.dst);
|
||||
height = drm_rect_height(&crtc_state->pch_pfit.dst);
|
||||
} else {
|
||||
width = pipe_mode->crtc_hdisplay;
|
||||
height = pipe_mode->crtc_vdisplay;
|
||||
}
|
||||
return skl_update_scaler(crtc_state, !crtc_state->hw.active,
|
||||
SKL_CRTC_INDEX,
|
||||
&crtc_state->scaler_state.scaler_id,
|
||||
crtc_state->pipe_src_w, crtc_state->pipe_src_h,
|
||||
width, height, NULL, 0,
|
||||
crtc_state->pch_pfit.enabled);
|
||||
}
|
||||
|
||||
/**
|
||||
* skl_update_scaler_plane - Stages update to scaler state for a given plane.
|
||||
* @crtc_state: crtc's scaler state
|
||||
* @plane_state: atomic plane state to update
|
||||
*
|
||||
* Return
|
||||
* 0 - scaler_usage updated successfully
|
||||
* error - requested scaling cannot be supported or other error condition
|
||||
*/
|
||||
int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
|
||||
struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct intel_plane *intel_plane =
|
||||
to_intel_plane(plane_state->uapi.plane);
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
|
||||
struct drm_framebuffer *fb = plane_state->hw.fb;
|
||||
int ret;
|
||||
bool force_detach = !fb || !plane_state->uapi.visible;
|
||||
bool need_scaler = false;
|
||||
|
||||
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
|
||||
if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
|
||||
fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
|
||||
need_scaler = true;
|
||||
|
||||
ret = skl_update_scaler(crtc_state, force_detach,
|
||||
drm_plane_index(&intel_plane->base),
|
||||
&plane_state->scaler_id,
|
||||
drm_rect_width(&plane_state->uapi.src) >> 16,
|
||||
drm_rect_height(&plane_state->uapi.src) >> 16,
|
||||
drm_rect_width(&plane_state->uapi.dst),
|
||||
drm_rect_height(&plane_state->uapi.dst),
|
||||
fb ? fb->format : NULL,
|
||||
fb ? fb->modifier : 0,
|
||||
need_scaler);
|
||||
|
||||
if (ret || plane_state->scaler_id < 0)
|
||||
return ret;
|
||||
|
||||
/* check colorkey */
|
||||
if (plane_state->ckey.flags) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"[PLANE:%d:%s] scaling with color key not allowed",
|
||||
intel_plane->base.base.id,
|
||||
intel_plane->base.name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Check src format */
|
||||
switch (fb->format->format) {
|
||||
case DRM_FORMAT_RGB565:
|
||||
case DRM_FORMAT_XBGR8888:
|
||||
case DRM_FORMAT_XRGB8888:
|
||||
case DRM_FORMAT_ABGR8888:
|
||||
case DRM_FORMAT_ARGB8888:
|
||||
case DRM_FORMAT_XRGB2101010:
|
||||
case DRM_FORMAT_XBGR2101010:
|
||||
case DRM_FORMAT_ARGB2101010:
|
||||
case DRM_FORMAT_ABGR2101010:
|
||||
case DRM_FORMAT_YUYV:
|
||||
case DRM_FORMAT_YVYU:
|
||||
case DRM_FORMAT_UYVY:
|
||||
case DRM_FORMAT_VYUY:
|
||||
case DRM_FORMAT_NV12:
|
||||
case DRM_FORMAT_XYUV8888:
|
||||
case DRM_FORMAT_P010:
|
||||
case DRM_FORMAT_P012:
|
||||
case DRM_FORMAT_P016:
|
||||
case DRM_FORMAT_Y210:
|
||||
case DRM_FORMAT_Y212:
|
||||
case DRM_FORMAT_Y216:
|
||||
case DRM_FORMAT_XVYU2101010:
|
||||
case DRM_FORMAT_XVYU12_16161616:
|
||||
case DRM_FORMAT_XVYU16161616:
|
||||
break;
|
||||
case DRM_FORMAT_XBGR16161616F:
|
||||
case DRM_FORMAT_ABGR16161616F:
|
||||
case DRM_FORMAT_XRGB16161616F:
|
||||
case DRM_FORMAT_ARGB16161616F:
|
||||
if (INTEL_GEN(dev_priv) >= 11)
|
||||
break;
|
||||
fallthrough;
|
||||
default:
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
|
||||
intel_plane->base.base.id, intel_plane->base.name,
|
||||
fb->base.id, fb->format->format);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cnl_coef_tap(int i)
|
||||
{
|
||||
return i % 7;
|
||||
}
|
||||
|
||||
static u16 cnl_nearest_filter_coef(int t)
|
||||
{
|
||||
return t == 3 ? 0x0800 : 0x3000;
|
||||
}
|
||||
|
||||
/*
|
||||
* Theory behind setting nearest-neighbor integer scaling:
|
||||
*
|
||||
* 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
|
||||
* The letter represents the filter tap (D is the center tap) and the number
|
||||
* represents the coefficient set for a phase (0-16).
|
||||
*
|
||||
* +------------+------------------------+------------------------+
|
||||
* |Index value | Data value coeffient 1 | Data value coeffient 2 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 00h | B0 | A0 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 01h | D0 | C0 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 02h | F0 | E0 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 03h | A1 | G0 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 04h | C1 | B1 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | ... | ... | ... |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 38h | B16 | A16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 39h | D16 | C16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 3Ah | F16 | C16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
* | 3Bh | Reserved | G16 |
|
||||
* +------------+------------------------+------------------------+
|
||||
*
|
||||
* To enable nearest-neighbor scaling: program scaler coefficents with
|
||||
* the center tap (Dxx) values set to 1 and all other values set to 0 as per
|
||||
* SCALER_COEFFICIENT_FORMAT
|
||||
*
|
||||
*/
|
||||
|
||||
static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
|
||||
enum pipe pipe, int id, int set)
|
||||
{
|
||||
int i;
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
|
||||
PS_COEE_INDEX_AUTO_INC);
|
||||
|
||||
for (i = 0; i < 17 * 7; i += 2) {
|
||||
u32 tmp;
|
||||
int t;
|
||||
|
||||
t = cnl_coef_tap(i);
|
||||
tmp = cnl_nearest_filter_coef(t);
|
||||
|
||||
t = cnl_coef_tap(i + 1);
|
||||
tmp |= cnl_nearest_filter_coef(t) << 16;
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
|
||||
tmp);
|
||||
}
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
|
||||
}
|
||||
|
||||
static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
|
||||
{
|
||||
if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
|
||||
return (PS_FILTER_PROGRAMMED |
|
||||
PS_Y_VERT_FILTER_SELECT(set) |
|
||||
PS_Y_HORZ_FILTER_SELECT(set) |
|
||||
PS_UV_VERT_FILTER_SELECT(set) |
|
||||
PS_UV_HORZ_FILTER_SELECT(set));
|
||||
}
|
||||
|
||||
return PS_FILTER_MEDIUM;
|
||||
}
|
||||
|
||||
static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
|
||||
int id, int set, enum drm_scaling_filter filter)
|
||||
{
|
||||
switch (filter) {
|
||||
case DRM_SCALING_FILTER_DEFAULT:
|
||||
break;
|
||||
case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
|
||||
cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
|
||||
break;
|
||||
default:
|
||||
MISSING_CASE(filter);
|
||||
}
|
||||
}
|
||||
|
||||
void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct intel_crtc_scaler_state *scaler_state =
|
||||
&crtc_state->scaler_state;
|
||||
struct drm_rect src = {
|
||||
.x2 = crtc_state->pipe_src_w << 16,
|
||||
.y2 = crtc_state->pipe_src_h << 16,
|
||||
};
|
||||
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
|
||||
u16 uv_rgb_hphase, uv_rgb_vphase;
|
||||
enum pipe pipe = crtc->pipe;
|
||||
int width = drm_rect_width(dst);
|
||||
int height = drm_rect_height(dst);
|
||||
int x = dst->x1;
|
||||
int y = dst->y1;
|
||||
int hscale, vscale;
|
||||
unsigned long irqflags;
|
||||
int id;
|
||||
u32 ps_ctrl;
|
||||
|
||||
if (!crtc_state->pch_pfit.enabled)
|
||||
return;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm,
|
||||
crtc_state->scaler_state.scaler_id < 0))
|
||||
return;
|
||||
|
||||
hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
|
||||
vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
|
||||
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
|
||||
id = scaler_state->scaler_id;
|
||||
|
||||
ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
|
||||
ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
||||
|
||||
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
|
||||
crtc_state->hw.scaling_filter);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
|
||||
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
|
||||
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
|
||||
x << 16 | y);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
|
||||
width << 16 | height);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
void
|
||||
skl_program_plane_scaler(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
const struct drm_framebuffer *fb = plane_state->hw.fb;
|
||||
enum pipe pipe = plane->pipe;
|
||||
int scaler_id = plane_state->scaler_id;
|
||||
const struct intel_scaler *scaler =
|
||||
&crtc_state->scaler_state.scalers[scaler_id];
|
||||
int crtc_x = plane_state->uapi.dst.x1;
|
||||
int crtc_y = plane_state->uapi.dst.y1;
|
||||
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
|
||||
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
|
||||
u16 y_hphase, uv_rgb_hphase;
|
||||
u16 y_vphase, uv_rgb_vphase;
|
||||
int hscale, vscale;
|
||||
u32 ps_ctrl;
|
||||
|
||||
hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
|
||||
&plane_state->uapi.dst,
|
||||
0, INT_MAX);
|
||||
vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
|
||||
&plane_state->uapi.dst,
|
||||
0, INT_MAX);
|
||||
|
||||
/* TODO: handle sub-pixel coordinates */
|
||||
if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
|
||||
!icl_is_hdr_plane(dev_priv, plane->id)) {
|
||||
y_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
y_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
|
||||
/* MPEG2 chroma siting convention */
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
|
||||
} else {
|
||||
/* not used */
|
||||
y_hphase = 0;
|
||||
y_vphase = 0;
|
||||
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
}
|
||||
|
||||
ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
|
||||
ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
|
||||
|
||||
skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
|
||||
plane_state->hw.scaling_filter);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
|
||||
(crtc_x << 16) | crtc_y);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
|
||||
(crtc_w << 16) | crtc_h);
|
||||
}
|
||||
|
||||
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
|
||||
{
|
||||
struct drm_device *dev = intel_crtc->base.dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
||||
|
||||
intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
|
||||
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function detaches (aka. unbinds) unused scalers in hardware
|
||||
*/
|
||||
void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
const struct intel_crtc_scaler_state *scaler_state =
|
||||
&crtc_state->scaler_state;
|
||||
int i;
|
||||
|
||||
/* loop through and disable scalers that aren't in use */
|
||||
for (i = 0; i < intel_crtc->num_scalers; i++) {
|
||||
if (!scaler_state->scalers[i].in_use)
|
||||
skl_detach_scaler(intel_crtc, i);
|
||||
}
|
||||
}
|
||||
|
||||
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < crtc->num_scalers; i++)
|
||||
skl_detach_scaler(crtc, i);
|
||||
}
|
29
drivers/gpu/drm/i915/display/skl_scaler.h
Normal file
29
drivers/gpu/drm/i915/display/skl_scaler.h
Normal file
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2020 Intel Corporation
|
||||
*/
|
||||
#ifndef INTEL_SCALER_H
|
||||
#define INTEL_SCALER_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
enum drm_scaling_filter;
|
||||
struct drm_i915_private;
|
||||
struct intel_crtc_state;
|
||||
struct intel_plane_state;
|
||||
struct intel_plane;
|
||||
enum pipe;
|
||||
|
||||
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
|
||||
|
||||
int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
|
||||
struct intel_plane_state *plane_state);
|
||||
|
||||
void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
|
||||
|
||||
void skl_program_plane_scaler(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state);
|
||||
void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
|
||||
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
|
||||
#endif
|
|
@ -14,6 +14,7 @@
|
|||
#include "intel_pm.h"
|
||||
#include "intel_psr.h"
|
||||
#include "intel_sprite.h"
|
||||
#include "skl_scaler.h"
|
||||
#include "skl_universal_plane.h"
|
||||
|
||||
static const u32 skl_plane_formats[] = {
|
||||
|
@ -1054,7 +1055,7 @@ skl_program_plane(struct intel_plane *plane,
|
|||
intel_plane_ggtt_offset(plane_state) + surf_addr);
|
||||
|
||||
if (plane_state->scaler_id >= 0)
|
||||
skl_program_scaler(plane, crtc_state, plane_state);
|
||||
skl_program_plane_scaler(plane, crtc_state, plane_state);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
|
|
@ -30,4 +30,8 @@ int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane);
|
|||
int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
|
||||
int *x, int *y, u32 *offset);
|
||||
|
||||
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
|
||||
enum plane_id plane_id);
|
||||
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -38,6 +38,7 @@
|
|||
#include "intel_fifo_underrun.h"
|
||||
#include "intel_panel.h"
|
||||
#include "intel_sideband.h"
|
||||
#include "skl_scaler.h"
|
||||
|
||||
/* return pixels in terms of txbyteclkhs */
|
||||
static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
|
||||
|
|
Loading…
Reference in a new issue