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drm/amdgpu: refine vce3.0 initialize.
1. disable vce cg when vce hw initialize. 2. initizlize vce clock to 10KHz fo dgpu, so no need to set bypass clock to vce. Change-Id: I934c2c4820cc95c1bfa2fa41ff0f40a0d3cd1c40 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
570272d229
commit
714b1f5371
2 changed files with 35 additions and 18 deletions
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@ -230,6 +230,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
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struct amdgpu_ring *ring;
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int idx, r;
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vce_v3_0_override_vce_clock_gating(adev, true);
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if (!(adev->flags & AMD_IS_APU))
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amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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@ -708,18 +712,6 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
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return 0;
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}
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static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
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{
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u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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if (enable)
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tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
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else
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tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
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WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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}
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static int vce_v3_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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@ -727,11 +719,6 @@ static int vce_v3_0_set_clockgating_state(void *handle,
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bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
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int i;
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if ((adev->asic_type == CHIP_POLARIS10) ||
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(adev->asic_type == CHIP_TONGA) ||
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(adev->asic_type == CHIP_FIJI))
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vce_v3_0_set_bypass_mode(adev, enable);
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if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
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return 0;
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@ -788,7 +788,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
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static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
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{
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/* todo */
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int r, i;
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struct atom_clock_dividers dividers;
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u32 tmp;
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r = amdgpu_atombios_get_clock_dividers(adev,
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COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
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ecclk, false, ÷rs);
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if (r)
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return r;
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for (i = 0; i < 100; i++) {
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if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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tmp = RREG32_SMC(ixCG_ECLK_CNTL);
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tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
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CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
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tmp |= dividers.post_divider;
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WREG32_SMC(ixCG_ECLK_CNTL, tmp);
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for (i = 0; i < 100; i++) {
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if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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return 0;
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}
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