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irqchip/gic: Warn if GICv3 system registers are enabled

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When using a GICv3 in compatibility (v2) mode, having GICv3 system
register access enabled is not really compliant with the architecture.

Warn if the firmware (or the hypervisor) has been lazy.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier 2015-09-30 12:01:16 +01:00
parent 963fcd4095
commit 76e52dd01c
1 changed files with 15 additions and 0 deletions
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15
drivers/irqchip/irq-gic.c
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@ -51,6 +51,19 @@
#include "irq-gic-common.h"
#ifdef CONFIG_ARM64
#include <asm/cpufeature.h>
static void gic_check_cpu_features(void)
{
WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
TAINT_CPU_OUT_OF_SPEC,
"GICv3 system registers enabled, broken firmware!\n");
}
#else
#define gic_check_cpu_features() do { } while(0)
#endif
union gic_base {
void __iomem *common_base;
void __percpu * __iomem *percpu_base;
@ -987,6 +1000,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
BUG_ON(gic_nr >= MAX_GIC_NR);
gic_check_cpu_features();
gic = &gic_data[gic_nr];
#ifdef CONFIG_GIC_NON_BANKED
if (percpu_offset) { /* Frankein-GIC without banked registers... */