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PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge
From very vague, ambiguous and incomplete information from Marvell we deduced that the 32-bit Aardvark register at address 0x4 (PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode in the Functional Specification (only for Endpoint mode), controls two 16-bit PCIe registers: Command Register and Status Registers of PCIe Root Port. This means that bit 2 controls bus mastering and forwarding of memory and I/O requests in the upstream direction. According to PCI specifications bits [0:2] of Command Register, this should be by default disabled on reset. So explicitly disable these bits at early setup of the Aardvark driver. Remove code which unconditionally enables all 3 bits and let kernel code (via pci_set_master() function) to handle bus mastering of Root PCIe Bridge via emulated PCI_COMMAND on emulated bridge. Link: https://lore.kernel.org/r/20211028185659.20329-5-kabel@kernel.org Fixes:8a3ebd8de3
("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org #b2a56469d5
("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access")
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95997723b6
commit
771153fc88
1 changed files with 38 additions and 16 deletions
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@ -31,9 +31,6 @@
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/* PCIe core registers */
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#define PCIE_CORE_DEV_ID_REG 0x0
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#define PCIE_CORE_CMD_STATUS_REG 0x4
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#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
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#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
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#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
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#define PCIE_CORE_DEV_REV_REG 0x8
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#define PCIE_CORE_PCIEXP_CAP 0xc0
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#define PCIE_CORE_ERR_CAPCTL_REG 0x118
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@ -514,6 +511,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
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advk_writel(pcie, reg, VENDOR_ID_REG);
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/* Disable Root Bridge I/O space, memory space and bus mastering */
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
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/* Set Advanced Error Capabilities and Control PF0 register */
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reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
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PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
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@ -612,19 +614,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_pcie_disable_ob_win(pcie, i);
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advk_pcie_train_link(pcie);
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/*
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* FIXME: The following register update is suspicious. This register is
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* applicable only when the PCI controller is configured for Endpoint
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* mode, not as a Root Complex. But apparently when this code is
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* removed, some cards stop working. This should be investigated and
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* a comment explaining this should be put here.
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*/
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
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PCIE_CORE_CMD_IO_ACCESS_EN |
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PCIE_CORE_CMD_MEM_IO_REQ_EN;
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advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
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}
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static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
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@ -753,6 +742,37 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
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return -ETIMEDOUT;
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}
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static pci_bridge_emul_read_status_t
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advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
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int reg, u32 *value)
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{
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struct advk_pcie *pcie = bridge->data;
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switch (reg) {
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case PCI_COMMAND:
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*value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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return PCI_BRIDGE_EMUL_HANDLED;
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default:
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return PCI_BRIDGE_EMUL_NOT_HANDLED;
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}
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}
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static void
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advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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int reg, u32 old, u32 new, u32 mask)
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{
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struct advk_pcie *pcie = bridge->data;
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switch (reg) {
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case PCI_COMMAND:
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advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
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break;
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default:
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break;
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}
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}
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static pci_bridge_emul_read_status_t
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advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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@ -854,6 +874,8 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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}
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static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
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.read_base = advk_pci_bridge_emul_base_conf_read,
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.write_base = advk_pci_bridge_emul_base_conf_write,
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.read_pcie = advk_pci_bridge_emul_pcie_conf_read,
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.write_pcie = advk_pci_bridge_emul_pcie_conf_write,
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};
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