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PCI: aardvark: Clear all MSIs at setup
We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT). Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs, to ensure that we don't start receiving spurious interrupts. Use this new mask in advk_pcie_handle_msi(); Link: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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1 changed files with 4 additions and 2 deletions
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@ -116,6 +116,7 @@
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
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#define PCIE_MSI_ALL_MASK GENMASK(31, 0)
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#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
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#define PCIE_MSI_DATA_MASK GENMASK(15, 0)
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@ -571,6 +572,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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/* Clear all interrupts */
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advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
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advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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@ -583,7 +585,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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/* Unmask all MSIs */
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advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
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advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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/* Enable summary interrupt for GIC SPI source */
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reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
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@ -1399,7 +1401,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
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msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
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msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
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msi_status = msi_val & ~msi_mask;
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msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
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for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
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if (!(BIT(msi_idx) & msi_status))
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