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pinctrl: renesas: rzg2l: Add support to get/set pin config for GPIO port pins
Add support to get/set pin config for GPIO port pins. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211110224622.16022-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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parent
d1189991c8
commit
7f13a4297b
1 changed files with 34 additions and 2 deletions
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@ -106,6 +106,7 @@
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#define PM_OUTPUT 0x2
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#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
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#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
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#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
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struct rzg2l_dedicated_configs {
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@ -424,6 +425,23 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
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return ret;
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}
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static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
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u32 cfg, u32 port, u8 bit)
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{
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u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
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u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
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u32 data;
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if (bit >= pincount || port >= pctrl->data->n_port_pins)
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return -EINVAL;
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data = pctrl->data->port_pin_configs[port];
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if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))
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return -EINVAL;
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return 0;
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}
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static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
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u8 bit, u32 mask)
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{
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@ -466,9 +484,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
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unsigned int *pin_data = pin->drv_data;
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unsigned int arg = 0;
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u32 port_offset = 0;
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unsigned long flags;
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void __iomem *addr;
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u32 port_offset;
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u32 cfg = 0;
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u8 bit = 0;
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@ -479,6 +497,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
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cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
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bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
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} else {
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cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
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port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
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bit = RZG2L_PIN_ID_TO_PIN(_pin);
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if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
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return -EINVAL;
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}
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switch (param) {
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@ -525,9 +550,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
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unsigned int *pin_data = pin->drv_data;
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enum pin_config_param param;
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u32 port_offset = 0;
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unsigned long flags;
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void __iomem *addr;
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u32 port_offset;
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unsigned int i;
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u32 cfg = 0;
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u8 bit = 0;
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@ -539,6 +564,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
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cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
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bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
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} else {
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cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
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port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
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bit = RZG2L_PIN_ID_TO_PIN(_pin);
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if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
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return -EINVAL;
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}
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for (i = 0; i < num_configs; i++) {
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