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pinctrl: renesas: rzg2l: Add helper functions to read/write pin config
Add helper functions to read/read modify write pin config. Switch to use helper functions for pins supporting PIN_CONFIG_INPUT_ENABLE capabilities. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211110224622.16022-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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parent
c76629a63b
commit
d1189991c8
1 changed files with 37 additions and 24 deletions
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@ -424,6 +424,39 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
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return ret;
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}
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static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
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u8 bit, u32 mask)
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{
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void __iomem *addr = pctrl->base + offset;
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/* handle _L/_H for 32-bit register read/write */
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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return (readl(addr) >> (bit * 8)) & mask;
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}
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static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
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u8 bit, u32 mask, u32 val)
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{
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void __iomem *addr = pctrl->base + offset;
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unsigned long flags;
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u32 reg;
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/* handle _L/_H for 32-bit register read/write */
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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reg = readl(addr) & ~(mask << (bit * 8));
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writel(reg | (val << (bit * 8)), addr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int _pin,
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unsigned long *config)
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@ -432,8 +465,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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enum pin_config_param param = pinconf_to_config_param(*config);
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const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
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unsigned int *pin_data = pin->drv_data;
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u32 port_offset = 0, reg;
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unsigned int arg = 0;
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u32 port_offset = 0;
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unsigned long flags;
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void __iomem *addr;
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u32 cfg = 0;
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@ -452,17 +485,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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case PIN_CONFIG_INPUT_ENABLE:
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if (!(cfg & PIN_CFG_IEN))
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return -EINVAL;
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spin_lock_irqsave(&pctrl->lock, flags);
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/* handle _L/_H for 32-bit register read/write */
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addr = pctrl->base + IEN(port_offset);
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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reg = readl(addr) & (IEN_MASK << (bit * 8));
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arg = (reg >> (bit * 8)) & 0x1;
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spin_unlock_irqrestore(&pctrl->lock, flags);
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arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);
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break;
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case PIN_CONFIG_POWER_SOURCE: {
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@ -502,7 +525,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
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unsigned int *pin_data = pin->drv_data;
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enum pin_config_param param;
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u32 port_offset = 0, reg;
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u32 port_offset = 0;
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unsigned long flags;
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void __iomem *addr;
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unsigned int i;
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@ -528,17 +551,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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if (!(cfg & PIN_CFG_IEN))
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return -EINVAL;
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/* handle _L/_H for 32-bit register read/write */
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addr = pctrl->base + IEN(port_offset);
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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reg = readl(addr) & ~(IEN_MASK << (bit * 8));
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writel(reg | (arg << (bit * 8)), addr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg);
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break;
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}
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