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powerpc/32s: Enhance readability of trap types
This patch makes use of trap types in head_book3s_32.S Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/bd80ace67757f489fc4ecdb76dd1a71511daba94.1618847273.git.christophe.leroy@csgroup.eu
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0f5eb28a6c
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2 changed files with 28 additions and 21 deletions
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@ -27,6 +27,7 @@
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#ifdef CONFIG_PPC_BOOK3S
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#define INTERRUPT_DOORBELL 0xa00
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#define INTERRUPT_PERFMON 0xf00
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#define INTERRUPT_ALTIVEC_UNAVAIL 0xf20
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#endif
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/* BookE/BookS/4xx/8xx */
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@ -57,6 +58,11 @@
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#define INTERRUPT_DATA_BREAKPOINT_8xx 0x1c00
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#define INTERRUPT_INST_BREAKPOINT_8xx 0x1d00
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/* 603 */
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#define INTERRUPT_INST_TLB_MISS_603 0x1000
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#define INTERRUPT_DATA_LOAD_TLB_MISS_603 0x1100
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#define INTERRUPT_DATA_STORE_TLB_MISS_603 0x1200
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#ifndef __ASSEMBLY__
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#include <linux/context_tracking.h>
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@ -31,6 +31,7 @@
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#include <asm/kvm_book3s_asm.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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#include <asm/interrupt.h>
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#include "head_32.h"
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@ -239,7 +240,7 @@ __secondary_hold_acknowledge:
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/* System reset */
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/* core99 pmac starts the seconary here by changing the vector, and
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putting it back to what it was (unknown_async_exception) when done. */
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EXCEPTION(0x100, Reset, unknown_async_exception)
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EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, unknown_async_exception)
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/* Machine check */
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/*
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@ -255,7 +256,7 @@ __secondary_hold_acknowledge:
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* pointer when we take an exception from supervisor mode.)
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* -- paulus.
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*/
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START_EXCEPTION(0x200, MachineCheck)
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START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
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EXCEPTION_PROLOG_0
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#ifdef CONFIG_PPC_CHRP
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mtspr SPRN_SPRG_SCRATCH2,r1
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@ -276,7 +277,7 @@ __secondary_hold_acknowledge:
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b interrupt_return
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/* Data access exception. */
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START_EXCEPTION(0x300, DataAccess)
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START_EXCEPTION(INTERRUPT_DATA_STORAGE, DataAccess)
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#ifdef CONFIG_PPC_BOOK3S_604
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BEGIN_MMU_FTR_SECTION
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mtspr SPRN_SPRG_SCRATCH2,r10
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@ -297,7 +298,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
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#endif
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1: EXCEPTION_PROLOG_0 handle_dar_dsisr=1
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EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2 0x300 DataAccess handle_dar_dsisr=1
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EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataAccess handle_dar_dsisr=1
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prepare_transfer_to_handler
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lwz r5, _DSISR(r11)
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andis. r0, r5, DSISR_DABRMATCH@h
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@ -310,7 +311,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
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/* Instruction access exception. */
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START_EXCEPTION(0x400, InstructionAccess)
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START_EXCEPTION(INTERRUPT_INST_STORAGE, InstructionAccess)
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mtspr SPRN_SPRG_SCRATCH0,r10
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mtspr SPRN_SPRG_SCRATCH1,r11
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mfspr r10, SPRN_SPRG_THREAD
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@ -330,7 +331,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
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andi. r11, r11, MSR_PR
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EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2 0x400 InstructionAccess
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EXCEPTION_PROLOG_2 INTERRUPT_INST_STORAGE InstructionAccess
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andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
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stw r5, _DSISR(r11)
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stw r12, _DAR(r11)
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@ -339,19 +340,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
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b interrupt_return
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/* External interrupt */
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EXCEPTION(0x500, HardwareInterrupt, do_IRQ)
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EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)
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/* Alignment exception */
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START_EXCEPTION(0x600, Alignment)
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EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1
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START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
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EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl alignment_exception
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REST_NVGPRS(r1)
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b interrupt_return
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/* Program check exception */
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START_EXCEPTION(0x700, ProgramCheck)
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EXCEPTION_PROLOG 0x700 ProgramCheck
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START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
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EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
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prepare_transfer_to_handler
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bl program_check_exception
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REST_NVGPRS(r1)
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@ -367,7 +368,7 @@ BEGIN_FTR_SECTION
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*/
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b ProgramCheck
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END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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EXCEPTION_PROLOG 0x800 FPUnavailable
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EXCEPTION_PROLOG INTERRUPT_FP_UNAVAIL FPUnavailable
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beq 1f
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bl load_up_fpu /* if from user, just load it up */
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b fast_exception_return
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@ -379,16 +380,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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#endif
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/* Decrementer */
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EXCEPTION(0x900, Decrementer, timer_interrupt)
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EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)
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EXCEPTION(0xa00, Trap_0a, unknown_exception)
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EXCEPTION(0xb00, Trap_0b, unknown_exception)
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/* System call */
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START_EXCEPTION(0xc00, SystemCall)
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SYSCALL_ENTRY 0xc00
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START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
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SYSCALL_ENTRY INTERRUPT_SYSCALL
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EXCEPTION(0xd00, SingleStep, single_step_exception)
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EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
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EXCEPTION(0xe00, Trap_0e, unknown_exception)
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/*
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@ -399,10 +400,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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* non-altivec kernel running on a machine with altivec just
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* by executing an altivec instruction.
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*/
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START_EXCEPTION(0xf00, PerformanceMonitorTrap)
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START_EXCEPTION(INTERRUPT_PERFMON, PerformanceMonitorTrap)
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b PerformanceMonitor
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START_EXCEPTION(0xf20, AltiVecUnavailableTrap)
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START_EXCEPTION(INTERRUPT_ALTIVEC_UNAVAIL, AltiVecUnavailableTrap)
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b AltiVecUnavailable
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__HEAD
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@ -410,7 +411,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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* Handle TLB miss for instruction on 603/603e.
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* Note: we get an alternate set of r0 - r3 to use automatically.
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*/
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. = 0x1000
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. = INTERRUPT_INST_TLB_MISS_603
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InstructionTLBMiss:
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/*
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* r0: scratch
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@ -476,7 +477,7 @@ InstructionAddressInvalid:
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/*
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* Handle TLB miss for DATA Load operation on 603/603e
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*/
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. = 0x1100
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. = INTERRUPT_DATA_LOAD_TLB_MISS_603
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DataLoadTLBMiss:
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/*
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* r0: scratch
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@ -554,7 +555,7 @@ DataAddressInvalid:
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/*
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* Handle TLB miss for DATA Store on 603/603e
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*/
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. = 0x1200
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. = INTERRUPT_DATA_STORE_TLB_MISS_603
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DataStoreTLBMiss:
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/*
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* r0: scratch
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