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ARC: [plat-arfpga] BVCI Latency Unit setup
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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2 changed files with 88 additions and 0 deletions
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@ -44,4 +44,36 @@ config ARC_SERIAL_BAUD
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help
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Baud rate for the ARC UART
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menuconfig ARC_HAS_BVCI_LAT_UNIT
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bool "BVCI Bus Latency Unit"
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depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
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help
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IP to add artifical latency to BVCI Bus Based FPGA builds.
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The default latency (even worst case) for FPGA is non-realistic
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(~10 SDRAM, ~5 SSRAM).
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config BVCI_LAT_UNITS
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hex "Latency Unit(s) Bitmap"
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default "0x0"
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depends on ARC_HAS_BVCI_LAT_UNIT
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help
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There are multiple Latency Units corresponding to the many
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interfaces of the system bus arbiter (both CPU side as well as
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the peripheral side).
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To add latency to ALL memory transaction, choose Unit 0, otherwise
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for finer grainer - interface wise latency, specify a bitmap (1 bit
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per unit) of all units. e.g. 1,2,12 will be 0x1003
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Unit 0 - System Arb and Mem Controller
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Unit 1 - I$ and System Bus
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Unit 2 - D$ and System Bus
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..
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Unit 12 - IDE Disk controller and System Bus
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config BVCI_LAT_CYCLES
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int "Latency Value in cycles"
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range 0 63
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default "30"
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depends on ARC_HAS_BVCI_LAT_UNIT
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endif
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@ -12,6 +12,7 @@
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/console.h>
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#include <linux/of_platform.h>
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#include <asm/setup.h>
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@ -19,6 +20,59 @@
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#include <asm/clk.h>
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#include <plat/memmap.h>
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/*-----------------------BVCI Latency Unit -----------------------------*/
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#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT
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int lat_cycles = CONFIG_BVCI_LAT_CYCLES;
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/* BVCI Bus Profiler: Latency Unit */
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static void __init setup_bvci_lat_unit(void)
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{
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#define MAX_BVCI_UNITS 12
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unsigned int i;
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unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE;
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const unsigned long units_req = CONFIG_BVCI_LAT_UNITS;
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const unsigned int REG_UNIT = 21;
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const unsigned int REG_VAL = 22;
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/*
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* There are multiple Latency Units corresponding to the many
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* interfaces of the system bus arbiter (both CPU side as well as
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* the peripheral side).
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*
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* Unit 0 - System Arb and Mem Controller - adds latency to all
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* memory trasactions
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* Unit 1 - I$ and System Bus
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* Unit 2 - D$ and System Bus
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* ..
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* Unit 12 - IDE Disk controller and System Bus
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*
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* The programmers model requires writing to lat_unit reg first
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* and then the latency value (cycles) to lat_value reg
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*/
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if (CONFIG_BVCI_LAT_UNITS == 0) {
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writel(0, base + REG_UNIT);
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writel(lat_cycles, base + REG_VAL);
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pr_info("BVCI Latency for all Memory Transactions %d cycles\n",
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lat_cycles);
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} else {
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for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) {
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writel(i + 1, base + REG_UNIT); /* loop is 0 based */
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writel(lat_cycles, base + REG_VAL);
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pr_info("BVCI Latency for Unit[%d] = %d cycles\n",
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(i + 1), lat_cycles);
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}
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}
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}
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#else
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static void __init setup_bvci_lat_unit(void)
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{
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}
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#endif
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/*----------------------- Platform Devices -----------------------------*/
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static unsigned long arc_uart_info[] = {
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@ -106,6 +160,8 @@ void __init arc_platform_early_init(void)
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{
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pr_info("[plat-arcfpga]: registering early dev resources\n");
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setup_bvci_lat_unit();
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arc_fpga_serial_init();
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}
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