mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-12 21:57:43 +00:00
Code Issues Releases Wiki Activity

- dts: mt8173: fix style convention for pinctrl node

Browse source 
- dts: mt8173: fix indentation for some nodes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVbDIeAAoJELQ5Ylss8dNDDLEP/0R4lmllKTNgCenHx2au9lKS
 m840xzhrLd5xbCRVPcr2+TU/lAf4NLrQH2x/GBVwh6x/GhkHDZj/2KFsP8k5ZRSn
 z69pM81anorDPGWKspBXf7LyHCMMP6yFjiFJ1b6llMtj6tUY1e0IEB/99zMrLatR
 suUpW/LVCeR9dqdMUdvZQh9hLYlMYWMvWsecEl5Si46i/32ilfxMqjmjyCuzx+K+
 9LRPHPaqceHu6SFe0T9BkNtGWLzUb7B5ElMThzNy0IEyvdaXEXNa7Rz5smbXd0ya
 KirZ6RKzgI4WnGWXT8SdD1Y6DRq3iMGGdaFIhExCZ5oyKNbnS0QEYAwHrq+lNAnK
 TQRUb+XYj5g1Dfpk5YjuprqlvKnED7+hdAGShkxLadds9SEQmGiRdGz1lvPXQcO7
 gfAMZYlwqmZjpvBFAiSlEgOUi0U0oy0WVsePGCpFPUNMQl7KCcyxXDLVNM/yK5tK
 ux7BbYqDq+ZSZfJ5VtDXdpzyR/2jg5I0HWbBRsvtG6EieJG7GrDnBvTAHRfWEQ/T
 YDap5uSWgle4+tqWTbR5qkWb8D+EoJzuLoYpgo1v0a0xdX+aLZvD6X5o2aKNe2DB
 PTemGkZI+ElnSn+Snh8XVztA0/jwES4JPX3MiBSnwypZ4EW29N5qttZb39tCxMfJ
 o6nNpjFf48Gh9zD9yaO0
 =ozvM
 -----END PGP SIGNATURE-----

Merge tag 'v4.1-next-arm64' of https://github.com/mbgg/linux-mediatek into next/dt

Merge "ARM: mediatek: arm64 updates for v4.2" from Matthias Brugger:

- dts: mt8173: fix style convention for pinctrl node
- dts: mt8173: fix indentation for some nodes

* tag 'v4.1-next-arm64' of https://github.com/mbgg/linux-mediatek:
  arm64: dts: mt8173: fix some indentation
  arm64: dts: mt8173: Fixup pinctrl nodes
This commit is contained in:
Arnd Bergmann 2015-06-01 17:58:53 +02:00
commit 810265812a
1 changed files with 22 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file

@ -91,13 +91,13 @@ timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
@ -106,14 +106,13 @@ soc {
compatible = "simple-bus";
ranges;
syscfg_pctl_a: syscfg_pctl_a@10005000 {
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
pio: pinctrl@0x10005000 {
/*
* Pinctrl access register at 0x10005000 through regmap.
* Register 0x1000b000 is used by EINT.
*/
pio: pinctrl@10005000 {
compatible = "mediatek,mt8173-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
pins-are-numbered;
gpio-controller;
@ -121,13 +120,18 @@ pio: pinctrl@0x10005000 {
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
syscfg_pctl_a: syscfg_pctl_a@10005000 {
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
@ -149,7 +153,7 @@ gic: interrupt-controller@10220000 {
uart0: serial@11002000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
@ -158,7 +162,7 @@ uart0: serial@11002000 {
uart1: serial@11003000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
@ -167,7 +171,7 @@ uart1: serial@11003000 {
uart2: serial@11004000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
@ -176,13 +180,12 @@ uart2: serial@11004000 {
uart3: serial@11005000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};
};