mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
Renesas ARM Based SoC Clock Updates for v3.16
SH Mobile shared clock code * Introduce shmobile_clk_workaround() r8a7791 (R-Car M2) SoC * Rename VSP1_SY clocks to VSP1_S * Correct the I2C clocks parents r8a7790 (R-Car H2) SoC * Remove old style audio clock * Rename VSP1_(SY|RT) clocks to VSP1_(S|R) * Fix the I2C clocks parents r8a7778 (R-Car M1) SoC * Remove old style audio clock -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.15 (GNU/Linux) iQIcBAABAgAGBQJTTxwIAAoJENfPZGlqN0++fygQAI+a2/56324u5uiT5lpGcmWh UHvDhNErnvPNWZzBox3dDq9+fAqRQNnfPrFV3lrhJsf/EycofOKA+l86bG9XXCYK GMEnjOgGwwl4QbyUD1I8D2UksnlkBnU+Msau+vafwQC9CgM2yqoMbKsM//GxEoww YQ1TQZpSDjNXOopnT7rXmIq6gP//GzafnfaPr7eKW/YRwAdrDJ7b3rAIfUMxBidO yxPew8etQHlD6HVeD/KYfZRt81KzHAeStM8VktSO9Q41ZxQ/rlEbkQwYVOYKkpi9 UthRC1pIG4xGibtYq7b0b3zMHkJLw/TVecLsOAP5Km90qcKeGZ6yBj3xmOGfyFJX LbcrD6HrCNuFs+wHKd6XwKyFKGvSit4WWgzMzP5AsCcMWtCG+AyF4Zrx7nyflaGy +f45No1heXAi0dGr/RgfsxcOnClXsgz49Cdf3xJLXoLzjECc/xufu+XteG+w+cBb JMU/UXOLVuX/JUa/ukPokaHNNWqWe9QvcsAf91L+Bba5D8MnYw1ZP0CfqyyR3Ox3 5wCK+lb7/uNKdlENS4QNJ/JfZBN0PBlf5EUscSMFHoPzWp0cHYeUGtYQ25jZIVTr VhzMmtU9YiHuqGMrh3Q2f0U0WbeoxBlIaEBO3FQK9maqlElZy+svoLg0px9jgZpB R5+ndfWrVRCW5x+tpp9D =bARP -----END PGP SIGNATURE----- Merge tag 'renesas-clock-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC Clock Updates for v3.16" from Simon Horman: SH Mobile shared clock code * Introduce shmobile_clk_workaround() r8a7791 (R-Car M2) SoC * Rename VSP1_SY clocks to VSP1_S * Correct the I2C clocks parents r8a7790 (R-Car H2) SoC * Remove old style audio clock * Rename VSP1_(SY|RT) clocks to VSP1_(S|R) * Fix the I2C clocks parents r8a7778 (R-Car M1) SoC * Remove old style audio clock * tag 'renesas-clock-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: remove old style audio clock ARM: shmobile: r8a7778: remove old style audio clock ARM: shmobile: r8a7791: Rename VSP1_SY clocks to VSP1_S ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R) ARM: shmobile: r8a7791: Fix the I2C clocks parents in legacy code ARM: shmobile: r8a7790: Fix the I2C clocks parents in legacy code ARM: shmobile: Introduce shmobile_clk_workaround() ARM: shmobile: r8a7791: Use rcar_gen2_read_mode_pins() helper Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
814789e2f1
10 changed files with 81 additions and 52 deletions
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@ -673,7 +673,7 @@ mstp1_clks: mstp1_clks@e6150134 {
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renesas,clock-indices = <
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R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
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R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
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R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
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R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
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>;
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clock-output-names =
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"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
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@ -688,7 +688,7 @@ mstp1_clks: mstp1_clks@e6150134 {
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renesas,clock-indices = <
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R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
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R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
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R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
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R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
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>;
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clock-output-names =
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"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
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@ -21,8 +21,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
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# Clock objects
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ifndef CONFIG_COMMON_CLK
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obj-y += clock.o
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ifndef CONFIG_COMMON_CLK
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obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o
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obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
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obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
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@ -175,10 +175,6 @@ static struct clk mstp_clks[MSTP_NR] = {
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static struct clk_lookup lookups[] = {
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/* main */
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CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
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CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
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CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
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CLKDEV_CON_ID("audio_clk_internal", &s1_clk),
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CLKDEV_CON_ID("shyway_clk", &s_clk),
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CLKDEV_CON_ID("peripheral_clk", &p_clk),
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@ -234,15 +230,15 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
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CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
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CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
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CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
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CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
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CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
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CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
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CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
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CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
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CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
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CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
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CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
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CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]),
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CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]),
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CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]),
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CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]),
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CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]),
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CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]),
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CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]),
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CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]),
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CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]),
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};
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void __init r8a7778_clock_init(void)
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@ -249,10 +249,10 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
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[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
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[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
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[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
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[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
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[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
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@ -294,10 +294,6 @@ static struct clk mstp_clks[MSTP_NR] = {
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
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CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
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CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
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CLKDEV_CON_ID("audio_clk_internal", &m2_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
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CLKDEV_CON_ID("main", &main_clk),
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@ -381,16 +377,16 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
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CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
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CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
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CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP1031]),
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CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP1030]),
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CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP1029]),
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CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP1028]),
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CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP1027]),
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CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP1026]),
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CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP1025]),
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CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP1024]),
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CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP1023]),
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CLKDEV_ICK_ID("scu.9", "rcar_sound", &mstp_clks[MSTP1022]),
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CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
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CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
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CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
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CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
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CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
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CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
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CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
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CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
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CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
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CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
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CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
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CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
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CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
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@ -25,6 +25,7 @@
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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#include <mach/rcar-gen2.h>
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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@ -43,8 +44,6 @@
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* see "p1 / 2" on R8A7791_CLOCK_ROOT() below
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*/
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#define MD(nr) (1 << nr)
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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@ -68,7 +67,6 @@
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#define MSTPSR9 IOMEM(0xe61509a4)
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#define MSTPSR11 IOMEM(0xe61509ac)
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#define MODEMR 0xE6160060
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#define SDCKCR 0xE6150074
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#define SD1CKCR 0xE6150078
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#define SD2CKCR 0xE615026c
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@ -190,12 +188,12 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
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[MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
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[MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
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[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
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[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
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[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
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[MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
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[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
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[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
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[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
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@ -295,14 +293,9 @@ static struct clk_lookup lookups[] = {
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void __init r8a7791_clock_init(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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u32 mode;
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u32 mode = rcar_gen2_read_mode_pins();
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int k, ret = 0;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
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@ -21,6 +21,32 @@
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#ifdef CONFIG_COMMON_CLK
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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void __init shmobile_clk_workaround(const struct clk_name *clks,
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int nr_clks, bool enable)
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{
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const struct clk_name *clkn;
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struct clk *clk;
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unsigned int i;
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for (i = 0; i < nr_clks; ++i) {
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clkn = clks + i;
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clk = clk_get(NULL, clkn->clk);
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if (!IS_ERR(clk)) {
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clk_register_clkdev(clk, clkn->con_id, clkn->dev_id);
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if (enable)
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clk_prepare_enable(clk);
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clk_put(clk);
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}
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}
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}
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#else /* CONFIG_COMMON_CLK */
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#include <linux/sh_clk.h>
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#include <linux/export.h>
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#include <mach/clock.h>
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@ -58,3 +84,5 @@ void __clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(__clk_put);
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#endif /* CONFIG_COMMON_CLK */
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@ -1,6 +1,21 @@
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#ifndef CLOCK_H
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#define CLOCK_H
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#ifdef CONFIG_COMMON_CLK
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/* temporary clock configuration helper for platform devices */
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struct clk_name {
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const char *clk;
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const char *con_id;
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const char *dev_id;
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};
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void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks,
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bool enable);
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#else /* CONFIG_COMMON_CLK */
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/* legacy clock implementation */
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unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
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extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
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|
@ -36,4 +51,5 @@ do { \
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(p)->div = d; \
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} while (0)
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#endif /* CONFIG_COMMON_CLK */
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#endif
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|
|
@ -33,8 +33,8 @@
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|||
#define R8A7790_CLK_TMU0 25
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||||
#define R8A7790_CLK_VSP1_DU1 27
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||||
#define R8A7790_CLK_VSP1_DU0 28
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#define R8A7790_CLK_VSP1_RT 30
|
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#define R8A7790_CLK_VSP1_SY 31
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||||
#define R8A7790_CLK_VSP1_R 30
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||||
#define R8A7790_CLK_VSP1_S 31
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||||
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/* MSTP2 */
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#define R8A7790_CLK_SCIFA2 2
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|
@ -32,7 +32,7 @@
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#define R8A7791_CLK_TMU0 25
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||||
#define R8A7791_CLK_VSP1_DU1 27
|
||||
#define R8A7791_CLK_VSP1_DU0 28
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||||
#define R8A7791_CLK_VSP1_SY 31
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||||
#define R8A7791_CLK_VSP1_S 31
|
||||
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||||
/* MSTP2 */
|
||||
#define R8A7791_CLK_SCIFA2 2
|
||||
|
|
Loading…
Reference in a new issue