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iommu/tegra-smmu: Do not use PAGE_SHIFT and PAGE_MASK
PAGE_SHIFT and PAGE_MASK are defined corresponding to the page size for CPU virtual addresses, which means PAGE_SHIFT could be a number other than 12, but tegra-smmu maintains fixed 4KB IOVA pages and has fixed [21:12] bit range for PTE entries. So this patch replaces all PAGE_SHIFT/PAGE_MASK references with the macros defined with SMMU_PTE_SHIFT. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200911071643.17212-2-nicoleotsuka@gmail.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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1 changed files with 10 additions and 4 deletions
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@ -130,6 +130,11 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
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#define SMMU_PDE_SHIFT 22
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1))
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#define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK)
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#define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT)
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#define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT))
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#define SMMU_PD_READABLE (1 << 31)
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#define SMMU_PD_WRITABLE (1 << 30)
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#define SMMU_PD_NONSECURE (1 << 29)
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@ -644,7 +649,7 @@ static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
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u32 *pte, dma_addr_t pte_dma, u32 val)
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{
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struct tegra_smmu *smmu = as->smmu;
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unsigned long offset = offset_in_page(pte);
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unsigned long offset = SMMU_OFFSET_IN_PAGE(pte);
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*pte = val;
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@ -726,7 +731,7 @@ __tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
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pte_attrs |= SMMU_PTE_WRITABLE;
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tegra_smmu_set_pte(as, iova, pte, pte_dma,
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__phys_to_pfn(paddr) | pte_attrs);
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SMMU_PHYS_PFN(paddr) | pte_attrs);
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return 0;
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}
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@ -790,7 +795,7 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
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pfn = *pte & as->smmu->pfn_mask;
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return PFN_PHYS(pfn);
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return SMMU_PFN_PHYS(pfn);
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}
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static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
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@ -1108,7 +1113,8 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
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smmu->dev = dev;
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smmu->mc = mc;
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smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
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smmu->pfn_mask =
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BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1;
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dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
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mc->soc->num_address_bits, smmu->pfn_mask);
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smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1;
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