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staging: iio: frequency: ad9832: Fix alignment for DMA safety 

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.  Whilst here, move the marking to cover
the whole union. That has no functional affect, but makes it slightly
easier to see what is going on.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220813160600.1157169-1-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-08-13 17:06:00 +01:00
parent 14a4d22ead
commit 83856aaab4
1 changed files with 2 additions and 2 deletions
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4
drivers/staging/iio/frequency/ad9832.c
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@ -112,10 +112,10 @@ struct ad9832_state {
* transfer buffers to live in their own cache lines.
*/
union {
__be16 freq_data[4]____cacheline_aligned;
__be16 freq_data[4];
__be16 phase_data[2];
__be16 data;
};
} __aligned(IIO_DMA_MINALIGN);
};
static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)