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wifi: rtw89: add DIG register struct to share common algorithm
Since control register address for DIG are different per IC, add a new struct rtw89_dig_regs in chip info for each IC to define their own address. Signed-off-by: Eric Huang <echuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220908051257.25353-2-pkshih@realtek.com
This commit is contained in:
parent
7dbdf65525
commit
87deaad9c9
5 changed files with 111 additions and 27 deletions
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@ -2553,6 +2553,22 @@ struct rtw89_imr_info {
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u32 tmac_imr_set;
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};
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struct rtw89_dig_regs {
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u32 seg0_pd_reg;
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u32 pd_lower_bound_mask;
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u32 pd_spatial_reuse_en;
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struct rtw89_reg_def p0_lna_init;
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struct rtw89_reg_def p1_lna_init;
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struct rtw89_reg_def p0_tia_init;
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struct rtw89_reg_def p1_tia_init;
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struct rtw89_reg_def p0_rxb_init;
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struct rtw89_reg_def p1_rxb_init;
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struct rtw89_reg_def p0_p20_pagcugc_en;
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struct rtw89_reg_def p0_s20_pagcugc_en;
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struct rtw89_reg_def p1_p20_pagcugc_en;
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struct rtw89_reg_def p1_s20_pagcugc_en;
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};
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struct rtw89_chip_info {
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enum rtw89_core_chip_id chip_id;
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const struct rtw89_chip_ops *ops;
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@ -2595,6 +2611,7 @@ struct rtw89_chip_info {
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const struct rtw89_phy_table *nctl_table;
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const struct rtw89_txpwr_table *byr_table;
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const struct rtw89_phy_dig_gain_table *dig_table;
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const struct rtw89_dig_regs *dig_regs;
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const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
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const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
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[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
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@ -3465,26 +3465,32 @@ static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
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static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
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{
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rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT,
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B_PATH0_LNA_INIT_IDX_MSK, lna_idx);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT,
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B_PATH1_LNA_INIT_IDX_MSK, lna_idx);
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const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
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rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr,
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dig_regs->p0_lna_init.mask, lna_idx);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr,
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dig_regs->p1_lna_init.mask, lna_idx);
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}
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static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
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{
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rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT,
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B_PATH0_TIA_INIT_IDX_MSK, tia_idx);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT,
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B_PATH1_TIA_INIT_IDX_MSK, tia_idx);
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const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
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rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr,
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dig_regs->p0_tia_init.mask, tia_idx);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr,
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dig_regs->p1_tia_init.mask, tia_idx);
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}
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static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
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{
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rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT,
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B_PATH0_RXB_INIT_IDX_MSK, rxb_idx);
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rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT,
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B_PATH1_RXB_INIT_IDX_MSK, rxb_idx);
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const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
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rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr,
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dig_regs->p0_rxb_init.mask, rxb_idx);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr,
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dig_regs->p1_rxb_init.mask, rxb_idx);
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}
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static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
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@ -3498,21 +3504,19 @@ static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
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set.lna_idx, set.tia_idx, set.rxb_idx);
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}
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static const struct rtw89_reg_def sdagc_config[4] = {
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{R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
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{R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
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{R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
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{R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
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};
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static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
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bool enable)
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{
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u8 i = 0;
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const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
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for (i = 0; i < ARRAY_SIZE(sdagc_config); i++)
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rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr,
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sdagc_config[i].mask, enable);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
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dig_regs->p0_p20_pagcugc_en.mask, enable);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
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dig_regs->p0_s20_pagcugc_en.mask, enable);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
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dig_regs->p1_p20_pagcugc_en.mask, enable);
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rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
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dig_regs->p1_s20_pagcugc_en.mask, enable);
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rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
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}
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@ -3539,6 +3543,7 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
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bool enable)
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{
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const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
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const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
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enum rtw89_bandwidth cbw = chan->band_width;
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struct rtw89_dig_info *dig = &rtwdev->dig;
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u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
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@ -3581,10 +3586,10 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
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"Dynamic PD th disabled, Set PD_low_bd=0\n");
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}
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rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK,
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pd_val);
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rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD,
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B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable);
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rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
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dig_regs->pd_lower_bound_mask, pd_val);
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rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
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dig_regs->pd_spatial_reuse_en, enable);
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if (!rtwdev->hal.support_cckpd)
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return;
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@ -3762,15 +3762,22 @@
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#define R_PATH0_RXB_INIT 0x4658
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#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
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#define R_PATH0_LNA_INIT 0x4668
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#define R_PATH0_LNA_INIT_V1 0x472C
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#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
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#define R_PATH0_BTG 0x466C
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#define B_PATH0_BTG_SHEN GENMASK(18, 17)
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#define R_PATH0_TIA_INIT 0x4674
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#define B_PATH0_TIA_INIT_IDX_MSK BIT(17)
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#define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0
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#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
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#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
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#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
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#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
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#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
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#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
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#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
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#define R_PATH0_RXB_INIT_V1 0x46A8
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#define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
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#define R_PATH0_G_LNA6_OP1DB_V1 0x4688
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#define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
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#define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694
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@ -3797,7 +3804,10 @@
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#define R_P0_AGC_CTL 0x4730
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#define B_P0_AGC_EN BIT(31)
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#define R_PATH1_LNA_INIT 0x473C
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#define R_PATH1_LNA_INIT_V1 0x4A80
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#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
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#define R_PATH0_TIA_INIT_V1 0x473C
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#define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9)
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#define R_PATH1_TIA_INIT 0x4748
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#define B_PATH1_TIA_INIT_IDX_MSK BIT(17)
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#define R_PATH1_BTG 0x4740
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@ -3807,8 +3817,12 @@
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#define R_PATH1_G_LNA6_OP1DB_V1 0x476C
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#define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
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#define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774
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#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
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#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
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#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
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#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
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#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
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#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
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#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
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#define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
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#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
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@ -3824,6 +3838,8 @@
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#define B_P1_NBIIDX_VAL GENMASK(11, 0)
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#define B_P1_NBIIDX_NOTCH_EN BIT(12)
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#define R_SEG0R_PD 0x481C
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#define R_SEG0R_PD_V1 0x4860
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#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
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#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29)
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#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
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#define R_2P4G_BAND 0x4970
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@ -3847,8 +3863,12 @@
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#define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
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#define R_CCK_FC0_INV_V1 0x4A20
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#define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
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#define R_PATH1_RXB_INIT_V1 0x4A5C
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#define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
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#define R_P1_AGC_CTL 0x4A9C
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#define B_P1_AGC_EN BIT(31)
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#define R_PATH1_TIA_INIT_V1 0x4AA8
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#define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
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#define R_PATH0_RXBB_V1 0x4AD4
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#define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
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#define R_PATH1_RXBB_V1 0x4AE0
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@ -453,6 +453,26 @@ static const struct rtw89_imr_info rtw8852a_imr_info = {
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.tmac_imr_set = B_AX_TMAC_IMR_SET,
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};
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static const struct rtw89_dig_regs rtw8852a_dig_regs = {
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.seg0_pd_reg = R_SEG0R_PD,
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.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
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.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
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.p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
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.p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
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.p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
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.p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
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.p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
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.p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
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.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
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B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
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.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
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B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
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.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
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B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
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.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
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B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
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};
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static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
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struct rtw8852a_efuse *map)
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{
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.txpwr_factor_rf = 2,
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.txpwr_factor_mac = 1,
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.dig_table = &rtw89_8852a_phy_dig_table,
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.dig_regs = &rtw8852a_dig_regs,
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.tssi_dbw_table = NULL,
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.support_chanctx_num = 1,
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.support_bands = BIT(NL80211_BAND_2GHZ) |
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@ -131,6 +131,26 @@ static const struct rtw89_imr_info rtw8852c_imr_info = {
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.tmac_imr_set = B_AX_TMAC_IMR_SET_V1,
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};
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static const struct rtw89_dig_regs rtw8852c_dig_regs = {
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.seg0_pd_reg = R_SEG0R_PD,
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.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
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.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
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.p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
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.p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
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.p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
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.p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
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.p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
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.p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
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.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1,
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B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
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.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1,
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B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
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.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1,
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B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
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.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1,
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B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
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};
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static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg);
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static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
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@ -2967,6 +2987,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.txpwr_factor_rf = 2,
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.txpwr_factor_mac = 1,
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.dig_table = NULL,
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.dig_regs = &rtw8852c_dig_regs,
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.tssi_dbw_table = &rtw89_8852c_tssi_dbw_table,
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.support_chanctx_num = 1,
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.support_bands = BIT(NL80211_BAND_2GHZ) |
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