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clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845
QUPv3 clocks support DFS and thus register the RCGs which require support for the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Use new macro, split out init structures so they don't have to be copied] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
cc4f6944d0
commit
8b69c6dba2
1 changed files with 153 additions and 96 deletions
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@ -396,18 +396,27 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
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{ }
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};
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static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
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.name = "gcc_qupv3_wrap0_s0_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
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.cmd_rcgr = 0x17034,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s0_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
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.name = "gcc_qupv3_wrap0_s1_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
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@ -416,12 +425,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s1_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
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.name = "gcc_qupv3_wrap0_s2_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
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@ -430,12 +441,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s2_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
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.name = "gcc_qupv3_wrap0_s3_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
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@ -444,12 +457,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s3_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
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.name = "gcc_qupv3_wrap0_s4_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
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@ -458,12 +473,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s4_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
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.name = "gcc_qupv3_wrap0_s5_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
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@ -472,12 +489,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s5_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
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.name = "gcc_qupv3_wrap0_s6_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
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@ -486,12 +505,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s6_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
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.name = "gcc_qupv3_wrap0_s7_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
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@ -500,12 +521,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s7_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
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.name = "gcc_qupv3_wrap1_s0_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
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@ -514,12 +537,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s0_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
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.name = "gcc_qupv3_wrap1_s1_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
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@ -528,12 +553,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s1_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
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.name = "gcc_qupv3_wrap1_s2_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
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@ -542,12 +569,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s2_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
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.name = "gcc_qupv3_wrap1_s3_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
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@ -556,12 +585,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s3_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
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.name = "gcc_qupv3_wrap1_s4_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s4_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
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.name = "gcc_qupv3_wrap1_s5_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s5_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
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.name = "gcc_qupv3_wrap1_s6_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s6_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
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};
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static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
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.name = "gcc_qupv3_wrap1_s7_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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};
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static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
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.hid_width = 5,
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.parent_map = gcc_parent_map_0,
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.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap1_s7_clk_src",
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.parent_names = gcc_parent_names_0,
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.num_parents = 4,
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.ops = &clk_rcg2_shared_ops,
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},
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.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
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};
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static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
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@ -3458,9 +3490,29 @@ static const struct of_device_id gcc_sdm845_match_table[] = {
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};
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MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
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static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
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DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
|
||||
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
|
||||
};
|
||||
|
||||
static int gcc_sdm845_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
|
||||
if (IS_ERR(regmap))
|
||||
|
@ -3470,6 +3522,11 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
|
|||
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
|
||||
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
|
||||
|
||||
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
|
||||
ARRAY_SIZE(gcc_dfs_clocks));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue