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dt-bindings: spi: Add Tegra Quad SPI device tree binding
This patch adds YAML based device tree binding document for Tegra Quad SPI driver. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-3-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
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Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra Quad SPI Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jonathan Hunter <jonathanh@nvidia.com>
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allOf:
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- $ref: "spi-controller.yaml#"
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properties:
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compatible:
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enum:
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- nvidia,tegra210-qspi
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- nvidia,tegra186-qspi
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- nvidia,tegra194-qspi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: qspi
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- const: qspi_out
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clocks:
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maxItems: 2
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resets:
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maxItems: 1
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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patternProperties:
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"@[0-9a-f]+":
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type: object
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properties:
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spi-rx-bus-width:
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enum: [1, 2, 4]
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spi-tx-bus-width:
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enum: [1, 2, 4]
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nvidia,tx-clk-tap-delay:
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description:
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Delays the clock going out to device with this tap value.
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Tap value varies based on platform design trace lengths from Tegra
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QSPI to corresponding slave device.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 31
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nvidia,rx-clk-tap-delay:
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description:
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Delays the clock coming in from the device with this tap value.
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Tap value varies based on platform design trace lengths from Tegra
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QSPI to corresponding slave device.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 255
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required:
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- reg
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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- resets
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/reset/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@70410000 {
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compatible = "nvidia,tegra210-qspi";
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reg = <0x70410000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA210_CLK_QSPI>,
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<&tegra_car TEGRA210_CLK_QSPI_PM>;
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clock-names = "qspi", "qspi_out";
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resets = <&tegra_car 211>;
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dmas = <&apbdma 5>, <&apbdma 5>;
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dma-names = "rx", "tx";
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flash@0 {
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compatible = "spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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nvidia,tx-clk-tap-delay = <0>;
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nvidia,rx-clk-tap-delay = <0>;
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};
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};
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