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Code Issues Releases Wiki Activity

drm/i915/dvo: Rename the "active data order" bits

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We have two sets of bits for DVO "data order" stuff. Rename
one set to ACT_DATA_ORDER to make it clear they are separate
bitfields.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221122120825.26338-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2022-11-22 14:08:21 +02:00
parent 5abd7d8d0e
commit 9710a5c14e
2 changed files with 6 additions and 6 deletions
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4
drivers/gpu/drm/i915/display/intel_dvo.c
View file

@ -288,10 +288,10 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
enum pipe pipe = crtc->pipe;
u32 dvo_val;
/* Save the data order, since I don't know what it should be set to. */
/* Save the active data order, since I don't know what it should be set to. */
dvo_val = intel_de_read(i915, DVO(port)) &
(DVO_DEDICATED_INT_ENABLE |
DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
DVO_BLANK_ACTIVE_HIGH;

8
drivers/gpu/drm/i915/i915_reg.h
View file

@ -2613,10 +2613,10 @@
#define DVO_VSYNC_TRISTATE (1 << 9)
#define DVO_HSYNC_TRISTATE (1 << 8)
#define DVO_BORDER_ENABLE (1 << 7)
#define DVO_DATA_ORDER_GBRG (1 << 6)
#define DVO_DATA_ORDER_RGGB (0 << 6)
#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
#define DVO_ACT_DATA_ORDER_GBRG (1 << 6)
#define DVO_ACT_DATA_ORDER_RGGB (0 << 6)
#define DVO_ACT_DATA_ORDER_GBRG_ERRATA (0 << 6)
#define DVO_ACT_DATA_ORDER_RGGB_ERRATA (1 << 6)
#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
#define DVO_BLANK_ACTIVE_HIGH (1 << 2)