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drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients based on the vco freq. v2: Split the original changes into multiple smaller patches based on review by Ville v3: Addressed Ville's review comments. Fixed the error introduced in v2. Clear the old bits before we modify those bits as part of RMW. v4: TDC target cnt is 10 bits and not 8 bits (Ville) Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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de3a0fde9a
commit
9cbe40c15a
2 changed files with 33 additions and 12 deletions
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@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
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#define _CHV_PLL_DW8_CH0 0x8020
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#define _CHV_PLL_DW8_CH1 0x81A0
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#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
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#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
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#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
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#define _CHV_PLL_DW9_CH0 0x8024
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@ -6159,10 +6159,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
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int pipe = crtc->pipe;
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int dpll_reg = DPLL(crtc->pipe);
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enum dpio_channel port = vlv_pipe_to_channel(pipe);
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u32 loopfilter, intcoeff;
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u32 loopfilter, tribuf_calcntr;
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u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
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u32 dpio_val;
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int refclk;
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int vco;
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bestn = pipe_config->dpll.n;
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bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
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@ -6170,7 +6170,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
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bestm2 = pipe_config->dpll.m2 >> 22;
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bestp1 = pipe_config->dpll.p1;
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bestp2 = pipe_config->dpll.p2;
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vco = pipe_config->dpll.vco;
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dpio_val = 0;
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loopfilter = 0;
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/*
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* Enable Refclk and SSC
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@ -6217,18 +6219,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
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vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
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/* Loop filter */
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refclk = i9xx_get_refclk(crtc, 0);
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loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
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2 << DPIO_CHV_GAIN_CTRL_SHIFT;
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if (refclk == 100000)
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intcoeff = 11;
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else if (refclk == 38400)
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intcoeff = 10;
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else
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intcoeff = 9;
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loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
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if (vco == 5400000) {
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loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
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loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
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loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
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tribuf_calcntr = 0x9;
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} else if (vco <= 6200000) {
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loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
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loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
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loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
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tribuf_calcntr = 0x9;
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} else if (vco <= 6480000) {
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loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
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loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
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loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
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tribuf_calcntr = 0x8;
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} else {
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/* Not supported. Apply the same limits as in the max case */
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loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
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loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
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loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
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tribuf_calcntr = 0;
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}
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vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
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dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
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dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
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dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
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vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
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/* AFC Recal */
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vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
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vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
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