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wifi: rtw89: pci: correct suspend/resume setting for variant chips
We find that suspend/resume tests cause 8852CE lost, because some pci registers are changed for 8852CE. So, correct them accordingly. Signed-off-by: Chin-Yen Lee <timlee@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220819064811.37700-6-pkshih@realtek.com
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1 changed files with 23 additions and 8 deletions
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@ -3650,14 +3650,20 @@ static int __maybe_unused rtw89_pci_suspend(struct device *dev)
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{
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struct ieee80211_hw *hw = dev_get_drvdata(dev);
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struct rtw89_dev *rtwdev = hw->priv;
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL,
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B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
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rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
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rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);
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rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
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rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1,
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B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG);
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL,
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B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
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rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1,
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B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG);
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} else {
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rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1,
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B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN);
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}
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return 0;
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}
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@ -3678,15 +3684,24 @@ static int __maybe_unused rtw89_pci_resume(struct device *dev)
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{
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struct ieee80211_hw *hw = dev_get_drvdata(dev);
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struct rtw89_dev *rtwdev = hw->priv;
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,
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B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
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rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
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rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);
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rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);
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rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1,
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B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG);
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,
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B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);
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rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1,
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B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG);
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} else {
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rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1,
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B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN);
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rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1,
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B_AX_SEL_REQ_ENTR_L1);
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}
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rtw89_pci_l2_hci_ldo(rtwdev);
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rtw89_pci_filter_out(rtwdev);
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rtw89_pci_link_cfg(rtwdev);
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rtw89_pci_l1ss_cfg(rtwdev);
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