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drm/amd/powerplay: add CI asics support to smumgr (v3)

Browse source 
This ports support for CI asics (Bonaire, Hawaii)
to the powerplay smumgr

v2: warning fix (Alex)
v3: squash in fix for thermal (Tom)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2017-09-08 19:34:33 +08:00 committed by Alex Deucher
parent 510c2558b9
commit 9f4b35411c
8 changed files with 2978 additions and 1 deletions
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2
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
View file

@ -5454,5 +5454,7 @@
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en_MASK 0x1
#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en__SHIFT 0
#endif /* SMU_7_0_1_SH_MASK_H */

1
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
View file

@ -33,6 +33,7 @@ struct pp_hwmgr;
#define smu_lower_32_bits(n) ((uint32_t)(n))
#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
extern const struct pp_smumgr_func ci_smu_funcs;
extern const struct pp_smumgr_func cz_smu_funcs;
extern const struct pp_smumgr_func iceland_smu_funcs;
extern const struct pp_smumgr_func tonga_smu_funcs;

2
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
View file

@ -4,7 +4,7 @@
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o ci_smc.o ci_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

2755
drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c Normal file
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File diff suppressed because it is too large Load diff

52
drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h Normal file
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@ -0,0 +1,52 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef CI_SMC_H
#define CI_SMC_H
#include <linux/types.h>
struct pp_smumgr;
struct pp_hwmgr;
struct amd_pp_profile;
int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
uint16_t msg, uint32_t parameter);
int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
int ci_init_smc_table(struct pp_hwmgr *hwmgr);
int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr);
uint32_t ci_get_offsetof(uint32_t type, uint32_t member);
uint32_t ci_get_mac_definition(uint32_t value);
int ci_process_firmware_header(struct pp_hwmgr *hwmgr);
int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
bool ci_is_dpm_running(struct pp_hwmgr *hwmgr);
int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request);
#endif

86
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c Normal file
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@ -0,0 +1,86 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include "linux/delay.h"
#include "smumgr.h"
#include "ci_smumgr.h"
#include "cgs_common.h"
#include "ci_smc.h"
static int ci_smu_init(struct pp_smumgr *smumgr)
{
int i;
struct ci_smumgr *ci_priv = NULL;
ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
if (ci_priv == NULL)
return -ENOMEM;
for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
ci_priv->activity_target[i] = 30;
smumgr->backend = ci_priv;
return 0;
}
static int ci_smu_fini(struct pp_smumgr *smumgr)
{
kfree(smumgr->backend);
smumgr->backend = NULL;
cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
return 0;
}
static int ci_start_smu(struct pp_smumgr *smumgr)
{
return 0;
}
const struct pp_smumgr_func ci_smu_funcs = {
.smu_init = ci_smu_init,
.smu_fini = ci_smu_fini,
.start_smu = ci_start_smu,
.check_fw_load_finish = NULL,
.request_smu_load_fw = NULL,
.request_smu_load_specific_fw = NULL,
.send_msg_to_smc = ci_send_msg_to_smc,
.send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
.get_offsetof = ci_get_offsetof,
.process_firmware_header = ci_process_firmware_header,
.init_smc_table = ci_init_smc_table,
.update_sclk_threshold = ci_update_sclk_threshold,
.thermal_setup_fan_table = ci_thermal_setup_fan_table,
.populate_all_graphic_levels = ci_populate_all_graphic_levels,
.populate_all_memory_levels = ci_populate_all_memory_levels,
.get_mac_definition = ci_get_mac_definition,
.initialize_mc_reg_table = ci_initialize_mc_reg_table,
.is_dpm_running = ci_is_dpm_running,
.populate_requested_graphic_levels = ci_populate_requested_graphic_levels,
};

78
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h Normal file
View file

@ -0,0 +1,78 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _CI_SMUMANAGER_H_
#define _CI_SMUMANAGER_H_
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 6
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8
#include "smu7_discrete.h"
#include <pp_endian.h>
#include "ppatomctrl.h"
struct ci_pt_defaults {
u8 svi_load_line_en;
u8 svi_load_line_vddc;
u8 tdc_vddc_throttle_release_limit_perc;
u8 tdc_mawt;
u8 tdc_waterfall_ctl;
u8 dte_ambient_temp_base;
u32 display_cac;
u32 bapm_temp_gradient;
u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
};
struct ci_mc_reg_entry {
uint32_t mclk_max;
uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
struct ci_mc_reg_table {
uint8_t last;
uint8_t num_entries;
uint16_t validflag;
struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
struct ci_smumgr {
uint32_t soft_regs_start;
uint32_t dpm_table_start;
uint32_t mc_reg_table_start;
uint32_t fan_table_start;
uint32_t arb_table_start;
uint32_t ulv_setting_starts;
struct SMU7_Discrete_DpmTable smc_state_table;
struct SMU7_Discrete_PmFuses power_tune_table;
const struct ci_pt_defaults *power_tune_defaults;
SMU7_Discrete_MCRegisters mc_regs;
struct ci_mc_reg_table mc_reg_table;
uint32_t activity_target[SMU7_MAX_LEVELS_GRAPHICS];
};
#endif

3
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
View file

@ -65,6 +65,9 @@ int smum_early_init(struct pp_instance *handle)
handle->smu_mgr = smumgr;
switch (smumgr->chip_family) {
case AMDGPU_FAMILY_CI:
smumgr->smumgr_funcs = &ci_smu_funcs;
break;
case AMDGPU_FAMILY_CZ:
smumgr->smumgr_funcs = &cz_smu_funcs;
break;