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drm/radeon/audio: write audio/video latency info for DCE6/8
Needed by the hda driver to properly set up synchronization on the audio side. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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3 changed files with 91 additions and 0 deletions
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@ -102,6 +102,49 @@ void dce6_afmt_select_pin(struct drm_encoder *encoder)
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AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
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}
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void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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u32 tmp = 0, offset;
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if (!dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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radeon_connector = to_radeon_connector(connector);
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break;
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}
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (connector->latency_present[1])
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tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
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AUDIO_LIPSYNC(connector->audio_latency[1]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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} else {
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if (connector->latency_present[0])
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tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
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AUDIO_LIPSYNC(connector->audio_latency[0]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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}
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
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}
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void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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@ -35,6 +35,8 @@
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extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
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extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
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extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
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extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
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struct drm_display_mode *mode);
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/*
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* update the N and CTS parameters for a given pixel clock rate
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@ -361,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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if (ASIC_IS_DCE6(rdev)) {
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dce6_afmt_select_pin(encoder);
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dce6_afmt_write_sad_regs(encoder);
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dce6_afmt_write_latency_fields(encoder, mode);
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} else {
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evergreen_hdmi_write_sad_regs(encoder);
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dce4_afmt_write_latency_fields(encoder, mode);
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@ -683,6 +683,51 @@
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* bit5 = 176.4 kHz
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* bit6 = 192 kHz
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*/
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#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
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# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
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# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
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/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
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* 0 = invalid
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* x = legal delay value
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* 255 = sync not supported
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*/
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#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
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# define HBR_CAPABLE (1 << 0) /* enabled by default */
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
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# define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
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# define PRODUCT_ID(x) (((x) & 0xffff) << 16)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
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# define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
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# define PORT_ID0(x) (((x) & 0xffffffff) << 0)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
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# define PORT_ID1(x) (((x) & 0xffffffff) << 0)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
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# define DESCRIPTION0(x) (((x) & 0xff) << 0)
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# define DESCRIPTION1(x) (((x) & 0xff) << 8)
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# define DESCRIPTION2(x) (((x) & 0xff) << 16)
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# define DESCRIPTION3(x) (((x) & 0xff) << 24)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
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# define DESCRIPTION4(x) (((x) & 0xff) << 0)
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# define DESCRIPTION5(x) (((x) & 0xff) << 8)
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# define DESCRIPTION6(x) (((x) & 0xff) << 16)
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# define DESCRIPTION7(x) (((x) & 0xff) << 24)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
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# define DESCRIPTION8(x) (((x) & 0xff) << 0)
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# define DESCRIPTION9(x) (((x) & 0xff) << 8)
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# define DESCRIPTION10(x) (((x) & 0xff) << 16)
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# define DESCRIPTION11(x) (((x) & 0xff) << 24)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
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# define DESCRIPTION12(x) (((x) & 0xff) << 0)
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# define DESCRIPTION13(x) (((x) & 0xff) << 8)
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# define DESCRIPTION14(x) (((x) & 0xff) << 16)
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# define DESCRIPTION15(x) (((x) & 0xff) << 24)
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#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
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# define DESCRIPTION16(x) (((x) & 0xff) << 0)
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# define DESCRIPTION17(x) (((x) & 0xff) << 8)
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#define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL 0x54
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# define AUDIO_ENABLED (1 << 31)
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