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b43: HT-PHY: add classifier control function
After comparing operations on reg 0xB on N and HT it seems to be the same register with similar ops. Implement them for HT-PHY. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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476069224d
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2 changed files with 37 additions and 5 deletions
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@ -157,6 +157,22 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
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* Various PHY ops
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**************************************************/
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static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
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{
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u16 tmp;
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u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
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B43_PHY_HT_CLASS_CTL_OFDM_EN |
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B43_PHY_HT_CLASS_CTL_WAITED_EN;
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tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
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tmp &= allowed;
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tmp &= ~mask;
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tmp |= (val & mask);
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b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
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return tmp;
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}
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static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
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{
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u8 i, j;
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@ -264,7 +280,15 @@ static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
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b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
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b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
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/* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
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if (new_channel->hw_value == 14) {
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b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
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b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
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} else {
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b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
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B43_PHY_HT_CLASS_CTL_OFDM_EN);
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if (new_channel->band == IEEE80211_BAND_2GHZ)
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b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
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}
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/* TODO: separated function? */
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for (i = 0; i < 3; i++) {
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@ -376,8 +400,11 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
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if (0) /* TODO: condition */
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; /* TODO: PHY op on reg 0x217 */
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b43_phy_read(dev, 0xb0); /* TODO: what for? */
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b43_phy_set(dev, 0xb0, 0x1);
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
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b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
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else
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b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
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B43_PHY_HT_CLASS_CTL_CCK_EN);
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b43_phy_set(dev, 0xb1, 0x91);
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b43_phy_write(dev, 0x32f, 0x0003);
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@ -456,9 +483,8 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
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b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
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b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
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/* TODO: PHY op on reg 0xb0 */
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/* TODO: Should we restore it? Or store it in global PHY info? */
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b43_phy_ht_classifier(dev, 0, 0);
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b43_phy_ht_read_clip_detection(dev, clip_state);
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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@ -12,6 +12,10 @@
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#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
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#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
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#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
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#define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
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#define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
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#define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */
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#define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */
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#define B43_PHY_HT_BW1 0x1CE
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#define B43_PHY_HT_BW2 0x1CF
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#define B43_PHY_HT_BW3 0x1D0
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@ -43,6 +47,8 @@
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#define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118)
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#define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119)
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#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
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/* Values for PHY registers used on channel switching */
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struct b43_phy_ht_channeltab_e_phy {
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