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MIPS: Lantiq: Rename CGU_SYS_VR9 register
This register is also used on other SoCs. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11383/ Patchwork: https://patchwork.linux-mips.org/patch/11397/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 5 additions and 4 deletions
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@ -4,6 +4,7 @@
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
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*/
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#include <linux/io.h>
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@ -25,8 +26,8 @@ static unsigned int ram_clocks[] = {
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/* legacy xway clock */
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#define CGU_SYS 0x10
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/* vr9 clock */
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#define CGU_SYS_VR9 0x0c
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/* vr9, ar10/grx390 clock */
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#define CGU_SYS_XRX 0x0c
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#define CGU_IF_CLK_VR9 0x24
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unsigned long ltq_danube_fpi_hz(void)
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@ -104,7 +105,7 @@ unsigned long ltq_vr9_cpu_hz(void)
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unsigned int cpu_sel;
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unsigned long clk;
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cpu_sel = (ltq_cgu_r32(CGU_SYS_VR9) >> 4) & 0xf;
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cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf;
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switch (cpu_sel) {
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case 0:
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@ -145,7 +146,7 @@ unsigned long ltq_vr9_fpi_hz(void)
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unsigned long clk;
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cpu_clk = ltq_vr9_cpu_hz();
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ocp_sel = ltq_cgu_r32(CGU_SYS_VR9) & 0x3;
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ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3;
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switch (ocp_sel) {
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case 0:
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