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watchdog: aspeed: Fix translation of reset mode to ctrl register
[ Upstream commitd2fc8db691
] Assert RESET_SYSTEM bit for any reset and set MODE field from reset type. The watchdog control register has a RESET_SYSTEM bit that is really closer to activate a reset, and RESET_SYSTEM_MODE field that chooses how much to reset. Before this patch, a node without these optional property would do a SOC reset, but a node with properties requesting a cpu or SOC reset would do nothing and a node requesting a system reset would do a SOC reset. Fixes:b7f0b8ad25
("drivers/watchdog: ASPEED reference dev tree properties for config") Signed-off-by: Milton Miller <miltonm@us.ibm.com> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
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commit
b5c7dedc84
1 changed files with 6 additions and 3 deletions
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@ -234,11 +234,14 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
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} else {
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} else {
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if (!strcmp(reset_type, "cpu"))
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if (!strcmp(reset_type, "cpu"))
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wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
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WDT_CTRL_RESET_SYSTEM;
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else if (!strcmp(reset_type, "soc"))
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else if (!strcmp(reset_type, "soc"))
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
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WDT_CTRL_RESET_SYSTEM;
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else if (!strcmp(reset_type, "system"))
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else if (!strcmp(reset_type, "system"))
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wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
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WDT_CTRL_RESET_SYSTEM;
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else if (strcmp(reset_type, "none"))
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else if (strcmp(reset_type, "none"))
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return -EINVAL;
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return -EINVAL;
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}
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}
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