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cxgb4: Pass in a Congestion Channel Map to t4_sge_alloc_rxq()
Passes a Congestion Channel Map to t4_sge_alloc_rxq() for the Ethernet RX Queues based on the MPS Buffer Group Map of the TX Channel rather than just the TX Channel Map. Also, in t4_sge_alloc_rxq() for T5, setting up the Congestion Manager values of the new RX Ethernet Queue is done by firmware now. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3 changed files with 45 additions and 0 deletions
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@ -2551,6 +2551,41 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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&fl->bar2_qid);
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refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
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}
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/* For T5 and later we attempt to set up the Congestion Manager values
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* of the new RX Ethernet Queue. This should really be handled by
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* firmware because it's more complex than any host driver wants to
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* get involved with and it's different per chip and this is almost
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* certainly wrong. Firmware would be wrong as well, but it would be
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* a lot easier to fix in one place ... For now we do something very
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* simple (and hopefully less wrong).
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*/
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if (!is_t4(adap->params.chip) && cong >= 0) {
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u32 param, val;
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int i;
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param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
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FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
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FW_PARAMS_PARAM_YZ_V(iq->cntxt_id));
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if (cong == 0) {
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val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X);
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} else {
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val =
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CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
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for (i = 0; i < 4; i++) {
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if (cong & (1 << i))
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val |=
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CONMCTXT_CNGCHMAP_V(1 << (i << 2));
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}
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}
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ret = t4_set_params(adap, adap->mbox, adap->fn, 0, 1,
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¶m, &val);
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if (ret)
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dev_warn(adap->pdev_dev, "Failed to set Congestion"
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" Manager Context for Ingress Queue %d: %d\n",
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iq->cntxt_id, -ret);
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}
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return 0;
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fl_nomem:
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@ -61,6 +61,15 @@
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#define SGE_TIMERREGS 6
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#define TIMERREG_COUNTER0_X 0
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/* Congestion Manager Definitions.
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*/
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#define CONMCTXT_CNGTPMODE_S 19
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#define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S)
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#define CONMCTXT_CNGCHMAP_S 0
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#define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S)
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#define CONMCTXT_CNGTPMODE_CHANNEL_X 2
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#define CONMCTXT_CNGTPMODE_QUEUE_X 1
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/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
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* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
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* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
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@ -1123,6 +1123,7 @@ enum fw_params_param_dmaq {
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FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
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FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
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FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
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FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
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};
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enum fw_params_param_dev_diag {
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