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drm/amd/pp: Drop wrapper functions for upper/lower_32_bits 

replace smu_upper_32_bits/smu_lower_32_bits with
the standard kernel macros

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-03-06 13:31:13 +08:00 committed by Alex Deucher
parent 819a3e9ab4
commit bb03c9c4a9
5 changed files with 28 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
View File

@ -26,11 +26,6 @@
#include "amd_powerplay.h"
#include "hwmgr.h"
#define smu_lower_32_bits(n) ((uint32_t)(n))
#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
enum AVFS_BTC_STATUS {
AVFS_BTC_BOOT = 0,
AVFS_BTC_BOOT_STARTEDSMU,

24
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
View File

@ -204,11 +204,11 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
reg_data = smu_lower_32_bits(info.mc_addr) &
reg_data = lower_32_bits(info.mc_addr) &
PHM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
reg_data = smu_upper_32_bits(info.mc_addr) &
reg_data = upper_32_bits(info.mc_addr) &
PHM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
@ -347,8 +347,8 @@ static int cz_smu_populate_single_scratch_task(
return -EINVAL;
}
task->addr.low = smu_lower_32_bits(cz_smu->scratch_buffer[i].mc_addr);
task->addr.high = smu_upper_32_bits(cz_smu->scratch_buffer[i].mc_addr);
task->addr.low = lower_32_bits(cz_smu->scratch_buffer[i].mc_addr);
task->addr.high = upper_32_bits(cz_smu->scratch_buffer[i].mc_addr);
task->size_bytes = cz_smu->scratch_buffer[i].data_size;
if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
@ -384,8 +384,8 @@ static int cz_smu_populate_single_ucode_load_task(
return -EINVAL;
}
task->addr.low = smu_lower_32_bits(cz_smu->driver_buffer[i].mc_addr);
task->addr.high = smu_upper_32_bits(cz_smu->driver_buffer[i].mc_addr);
task->addr.low = lower_32_bits(cz_smu->driver_buffer[i].mc_addr);
task->addr.high = upper_32_bits(cz_smu->driver_buffer[i].mc_addr);
task->size_bytes = cz_smu->driver_buffer[i].data_size;
return 0;
@ -613,11 +613,11 @@ static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi,
smu_upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));
upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo,
smu_lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));
lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table);
@ -640,11 +640,11 @@ static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi,
smu_upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));
upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo,
smu_lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));
lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table);
@ -675,11 +675,11 @@ static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrHi,
smu_upper_32_bits(cz_smu->toc_buffer.mc_addr));
upper_32_bits(cz_smu->toc_buffer.mc_addr));
cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrLo,
smu_lower_32_bits(cz_smu->toc_buffer.mc_addr));
lower_32_bits(cz_smu->toc_buffer.mc_addr));
cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);

8
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
View File

@ -169,11 +169,11 @@ int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
"Invalid SMU Table Length!", return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
smu_upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
smu_lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
@ -206,12 +206,12 @@ int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
smu_upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
smu_lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL;);
PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,

12
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
View File

@ -369,8 +369,8 @@ static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
if (!result) {
entry->version = info.fw_version;
entry->id = (uint16_t)fw_type;
entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
entry->image_addr_high = upper_32_bits(info.mc_addr);
entry->image_addr_low = lower_32_bits(info.mc_addr);
entry->meta_data_addr_high = 0;
entry->meta_data_addr_low = 0;
@ -412,10 +412,10 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
if (!cgs_is_virtualization_enabled(hwmgr->device)) {
smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_HI,
smu_upper_32_bits(smu_data->smu_buffer.mc_addr));
upper_32_bits(smu_data->smu_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_LO,
smu_lower_32_bits(smu_data->smu_buffer.mc_addr));
lower_32_bits(smu_data->smu_buffer.mc_addr));
}
fw_to_load = UCODE_ID_RLC_G_MASK
+ UCODE_ID_SDMA0_MASK
@ -472,8 +472,8 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_upper_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_lower_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
pr_err("Fail to Request SMU Load uCode");

12
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
View File

@ -230,10 +230,10 @@ int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
"Invalid SMU Table Length!", return -EINVAL);
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
smu_upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
smu_lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id);
@ -267,10 +267,10 @@ int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
smu_upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
smu_lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id);
@ -337,10 +337,10 @@ int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) {
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetToolsDramAddrHigh,
smu_upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));
upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));
vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetToolsDramAddrLow,
smu_lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));
lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));
}
return 0;
}