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drm/amdgpu/sdma: switch to amdgpu_sdma_ras_late_init helper function
amdgpu_sdma_ras_late_init is used to init sdma specfic ras debugfs/sysfs node and sdma specific interrupt handler. It can be shared among sdma generations Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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6caeee7a70
commit
bfcf62c2a5
3 changed files with 55 additions and 41 deletions
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@ -23,6 +23,7 @@
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#include "amdgpu.h"
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#include "amdgpu.h"
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#include "amdgpu_sdma.h"
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#include "amdgpu_sdma.h"
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#include "amdgpu_ras.h"
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#define AMDGPU_CSA_SDMA_SIZE 64
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#define AMDGPU_CSA_SDMA_SIZE 64
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/* SDMA CSA reside in the 3rd page of CSA */
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/* SDMA CSA reside in the 3rd page of CSA */
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@ -83,3 +84,54 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
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return csa_mc_addr;
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return csa_mc_addr;
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}
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}
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int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
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void *ras_ih_info)
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{
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int r, i;
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struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
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struct ras_fs_if fs_info = {
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.sysfs_name = "sdma_err_count",
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.debugfs_name = "sdma_err_inject",
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};
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if (!ih_info)
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return -EINVAL;
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if (!adev->sdma.ras_if) {
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adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->sdma.ras_if)
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return -ENOMEM;
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adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
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adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->sdma.ras_if->sub_block_index = 0;
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strcpy(adev->sdma.ras_if->name, "sdma");
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}
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fs_info.head = ih_info->head = *adev->sdma.ras_if;
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r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
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&fs_info, ih_info);
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if (r)
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goto free;
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if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
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for (i = 0; i < adev->sdma.num_instances; i++) {
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r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
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AMDGPU_SDMA_IRQ_INSTANCE0 + i);
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if (r)
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goto late_fini;
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}
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} else {
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r = 0;
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goto free;
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}
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return 0;
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late_fini:
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amdgpu_ras_late_fini(adev, adev->sdma.ras_if, ih_info);
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free:
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kfree(adev->sdma.ras_if);
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adev->sdma.ras_if = NULL;
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return r;
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}
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@ -104,4 +104,6 @@ struct amdgpu_sdma_instance *
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amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
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amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
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int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
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int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
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uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
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uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
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int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
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void *ras_ih_info);
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#endif
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#endif
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@ -1699,48 +1699,8 @@ static int sdma_v4_0_late_init(void *handle)
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struct ras_ih_if ih_info = {
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struct ras_ih_if ih_info = {
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.cb = sdma_v4_0_process_ras_data_cb,
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.cb = sdma_v4_0_process_ras_data_cb,
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};
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};
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struct ras_fs_if fs_info = {
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.sysfs_name = "sdma_err_count",
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.debugfs_name = "sdma_err_inject",
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};
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int r, i;
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if (!adev->sdma.ras_if) {
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return amdgpu_sdma_ras_late_init(adev, &ih_info);
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adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->sdma.ras_if)
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return -ENOMEM;
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adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
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adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->sdma.ras_if->sub_block_index = 0;
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strcpy(adev->sdma.ras_if->name, "sdma");
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}
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fs_info.head = ih_info.head = *adev->sdma.ras_if;
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r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
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&fs_info, &ih_info);
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if (r)
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goto free;
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if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
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for (i = 0; i < adev->sdma.num_instances; i++) {
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r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
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AMDGPU_SDMA_IRQ_INSTANCE0 + i);
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if (r)
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goto late_fini;
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}
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} else {
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/* free sdma ras_if if sdma ras is not supported */
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r = 0;
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goto free;
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}
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return 0;
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late_fini:
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amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
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free:
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kfree(adev->sdma.ras_if);
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adev->sdma.ras_if = NULL;
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return r;
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}
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}
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static int sdma_v4_0_sw_init(void *handle)
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static int sdma_v4_0_sw_init(void *handle)
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